公开(公告)号：DE1111430B

公开(公告)日：1961-07-20

申请号：DEI0009980

申请日：1955-03-21

Applicant: IBM DEUTSCHLAND

Inventor： ROCHESTER NATHANIEL ,  BASHE CHARLES JULIAN ,  BUCHHOLZ WERNER ,  CRAGO ROBERT PAUL ,  FOX PHILIP EVERETT ,  HADDAD JERRIER ABDO ,  PHELPS BYRON EUGENE

IPC: G06F15/78

Abstract: 800,505. Digital electric calculating-apparatus; electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 18, 1955 [March 22, 1954], No. 7918/55. Class 106 (1). Electronic data processing apparatus includes input and output devices interconnected by a computer which employs variable length words, the lengths being demarcated by special coded characters. General. The electronic computer illustrated in Figs. 1a and 1b comprises a C.R.T. memory M, an accumulator including a C.R.T. store AS, and input/output magnetic tape units T. Words comprise a variable number of coded characters each represented by seven bits, Fig. 1c, comprising four numerical bits 1, 2, 4, 8, two zone bits A, B and a redundancy check bit C such as to make the total of " 1 "s in a character always odd. Numbers are in decimal form and have their digits represented in the excess-three code, the zone bits being "0." Words are separated by field marks " +," "-," Fig. 1c, the mark " - " being used only for numbers stored in the memory to indicate a negative sign. In the accumulator store, a negative sign is indicated by numerical " 9 " with " + " field mark zone digits. The field marks and other special characters are detected by recognition circuits CRC associated with two characters registers CR1, CR2, Fig. 1b, which receive characters as they are read out from the memory or accumulator store via main bus MB or accumulator storage bus AB, and also form a buffer between the memory and the tape units. The memory comprises 50 pairs of C.R.T.s; a pair is selected by unit selector US and a " left " or " right " C.R.T. of this pair by memory left/right control MC. The beam in the selected C.R.T. may be deflected to one of 100 character positions by memory deflection circuits MD. The circuits US, MC, MD are controlled by the portions indicated of a 4-decimal-digit address through memory switch MS. A word location is given by the address of the "right-hand " field mark (the one with the higher address number); e.g. the address of the number 123, 456, Fig. 1h, is 0037. Transfer to and from tape (writing and reading) is effected in the order of increasing address numbers (" left to right "), but transfer between the memory and the accumulator is effected in the reverse order (" right to left "). The accumulator store AS, which normally stores one word only, comprises a single C.R.T. having 100 character positions selected by deflection circuits ASD controlled by 2-digit addresses through switch ASS, addresses normally being selected in ascending order. A separate computer cycle is provided for dealing with each character, timing control signals being obtained from clock C and waveform generator WG. An instruction word, e.g. the word at address 0008, Fig. 1h, always comprises 6 characters, viz., an operation-defining character, an " address " portion (4 characters or digits) and a field mark, and is read out from the memory in ascending address order (operation character first). The addresses are sequentially set up in a programme counter PC (in a 1, 2, 2, 4 code) during the 6 successive character cycles of " instruction time," the computer being controlled by instruction timer IT to pass the operation character to interpreter II and the address digits via memory address translator MAT to a register MAR operating in the 1, 2, 2, 4 code. At the commencement of the subsequent " execution time," in which a timer ET is selected to carry out the instruction, the address in register MAR is transferred to counter MAC and normally applied via code ambiguity eliminator MAE to the switch MS to select a required memory location, and the amount registered on a two-decimal-digit starting point counter SPC may be transposed to an accumulator storage address counter AAC and applied via ambiguity eliminator ASAE to switch ASS to select an accumulator location when required. During subsequent execution character cycles, the count in MAC may be stepped down and the count in AAC stepped up to select successive character positions in the memory and accumulator store. Words from M and AS may be sent character by character to the comparator adder time/complement circuits CATC to perform arithmetic and other operations. The flow of information is controlled by routing circuits R. During a portion of each character cycle a regeneration counter RC is effective systematically to regenerate all the stored bits in the C.R.T.s, 50 tubes (one in each pair) being regenerated simultaneously in the main memory M. In some instructions, the memory is not used, and the " address " number in MAC is employed, e.g. to determine how the word stored in AS is to be modified, or to select, through in/out unit selector IOS, one of the tape or other input/ output units. The character emitter CE emits timed pulses representing certain numeral and other characters. The electronic circuits consist primarily of Eccles-Jordan double triode trigger circuits (T), coincidence switches (S) which usually produce a negative output in response to two positive inputs, diode AND and OR circuits, inverters (I) and cathode followers (CF); circuit diagrams for these components are given in the Specification. The computer is described below under the following headings: (1) Clock and waveform generator; timing signal rotation. (2) Basic counter. (3) Ambiguity eliminator. (4) Input/Output. (5) Character Registers and Character Recognition Circuits. (6) Memory address translator and register. (7) Memory address counter and ambiguity eliminator. (8) Programme counter. (9) Regeneration counter. (10) Memory and associated selection circuits. (11) Accumulator storage and associated circuits. (12) Memory and accumulator sign circuits. (13) Comparator, adder, true complement and associated circuits. (14) Adder and complementer. (15) Instruction timer; sequence of events during instruction time. (16) Instruction interpreter. (17) Routing circuits. (18) Execution timers; instructions. (19) Add or subtract instruction. (20) Reset add and subtract instructions. (21) Add to memory instruction. (22) Compare instruction. (23) Multiplication. (24) Division. (25) Instructions involving accumulator, store but not memory, rounding off; positioning decimal point. (26) " Store "-instruction. (27) Transfer of control instructions. (28) Tape instructions. (1) Clock and waveform generator; timing signal notation. The clock C, Fig. 1b, comprises a 1 mc/s. oscillator and a pulse distributing circuit similar to that of Specification 750,259 for defining regeneration (G), and read (R) and write (W) periods in a character cycle. The computer may be held in the " G " portion of the cycle under control of a " repeat regeneration" signal. The clock controls waveform generator circuits WG which develop timing signals such as those shown in Figs. 2c and 2i. Signals are denoted by the number of microseconds their leading edges occur after an index time G0-W7 and by their duration (D); e.g. the pulse L202, Fig. 2i, would be denoted WO1 (D2) meaning a pulse starting 1 Ás. after W0 and lasting 2 Ás. A train of pulses may also be denoted; e.g. R22 (D1)4 indicates 4 pulses each of 1 Ás. duration and starting 2 Ás. after R2 and succeeding index times (L203, Fig. 21). An inverted or complementary signal is indicated by c; e.g. L124c is a positive pulse coinciding with L124, Fig. 2c. (2) Basic counter. A decimal counting circuit CT1, Fig. 1d, comprises four double-triode triggers 101, 102, 103, 104 having weighted values 1, 2 (called 2C), 2, 4 respectively. The triggers may be reset to the " off " or " O " condition (right triode conducting) by a positive pulse at 11, inverted in 131 and applied through diodes 133-136 to the right anodes. Trigger 101 responds to negative input pulses at 15 and, for every second pulse, supplies a negative output pulse to diodes 105 and 107 connected respectively via line 107a to the right-hand input only of trigger 102 and via diode 110 and line 112 to both inputs of 103. Thus, after the second input pulse, trigger 102 is switched " on " and applies a positive gating potential via resistor 108 to diode 107 to allow subsequent pulses from 101 to switch trigger 103. Triggers 101, 103, 104 then operate in normal binary fashion until trigger 104 is switched back to " O " in response to the tenth input pulse, when the negative pulse from its right anode is applied via diode 116 to carry output terminal 27, and to line 118 to reset trigger 102. A value may be entered also in parallel, during a " dumping " operation, by selectively applying "1"-representing negative pulses to terminals 16-19. The registered value may be changed to its 9's complement by a negative pulse applied via 13 to line 126 to switch all the - triggers to the opposite condition, the connections between the triggers being inhibited by applying a positive signal at 12 to inverter 121 so as to drive line 122 negative. Output terminals 21-26 enable the registered value to be read out. After the complementing, and possibly after parallel entry, the representation of any value between 2 and 7 will be different from that obtained during normal stepping of the counter. This alternative representation is translated into the normal one in an ambiguity eliminator (described below). A simplified counter CT2 (Fig. 1e, not shown) having no provision for complementing, also is employed. (3) Ambiguity eliminator. The circuit AE, Fig. 1f, is a code interpreting circuit which receives respectively from terminals 21, 23-26 of a counter such as CT1, Fig. 1d, a negative input at 16 when the " 1 " trigger is " on," positive inputs at 17, 18 when the " 2 " triggers (102 and 103 respectively) are " on," and a positive input at 19 or 20 according to whether the "4" trigger is " off " or " on," and supplies positive outputs selectively to 21-24, corresponding to the weighted values 1, 2G, 2, 4, to represen

公开(公告)号：DE977604C

公开(公告)日：1967-07-20

申请号：DEI0010417

申请日：1955-07-13

Applicant: IBM DEUTSCHLAND

Inventor： BUCHHOLZ WERNER ,  WHITNEY GORDON EARLE

IPC: G06F3/00 ,  G06F3/08

公开(公告)号：DE1119566B

公开(公告)日：1961-12-14

申请号：DEI0007832

申请日：1953-10-24

Applicant: IBM DEUTSCHLAND

Inventor： BUCHHOLZ WERNER ,  DEUTSCHLE CECIL ALBERT ,  CRAWFORD DAVID JAMES

IPC: G06F9/00 ,  G06F15/10 ,  G06K7/00

Abstract: 753,333. Electric digital-data-storage apparatus; electronic counting-apparatus; recording- apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 22, 1953 [Oct. 25, 1952], No. 29188/53. Classes 106 (1) and 106 (4). In a data storage system comprising a magnetic storage device, means for transferring discrete items of data to different addresses on the device during relative movement between the device and the transferring means, and means for selecting a single address, the address selecting means comprises a single address store, and is controlled by means producing an indication of the instantaneous relative positions of the device and transferring means, for selecting a first address and for automatically selecting subsequent addresses without introduction of further addresses into the address store. General arrangement.-The magnetic storage system described is for use with a computer, cared " main machine (not described in detail), and comprises two magnetic drums each divided into two " logical drums." Each of the latter comprises 36 tracks for storing in parallel 36-digit binary numbers, a sync track containing a magnetised spot for marking each of the 2048 digit positions on the storage tracks, and an index track containing a single spot for defining a start position. Before the storage system can operate it must receive three " instructions " from the main machine, viz. : (1) Read Drum or Write Drum Select, which selects the required one of the four logical drums and determines whether data is to be read from or written on the drum; (2) Set Drum, which controls entry of a required first address on the drum from an address register (not shown) into the drum counter 35-45, Fig. 32b; and (3) Copy, which initiates the required read or write operation. If the Copy instruction is repeated, further addresses on the drum will be automatically selected. Fig. 8 illustrates the principle of operation. After the drum 20 passes the start position relative to the readwrite head H, timing pulses obtained from the sync track are applied to the drum counter comprising a series of 11 bi-stable triode trigger circuits, representing powers of 2 as indicated, on which the required address has been previously registered. When the counter produces an " end carry," an output pulse is obtained from a switching circuit S which pulse effects the required read or write operation, the addresses being so located on the drum that the required first address will then be opposite the head H. The timing pulses continue to be applied to the counter, and the circuit S is now arranged to be responsive to " middle carries," produced from the output of the first 7 triggers once for every 128 input pulses, whereby further consecutively numbered addresses, spaced 128 positions apart, are made available. Also, since those timing pulses which coincide in time with the index track pulses (one for each revolution of the drum) are not applied to the counter, a precession effect is obtained whereby if, e.g., addresses 16, 17, &c. were selected during the first drum revolution, addresses 32, 33, &c. would be selected during the second and so on, all the addresses on the drum being thus made available in turn. The address-selecting circuits shown in block diagrammatic form in Figs. 32a-32d (of which circuit details are given in the Specification), consist primarily of crosscoupled double triodes forming bi-stable trigger circuits T and single-shot multivibrators SS, triode inverting circuits I, diode AND and OR pulse-gating circuits, and drum-selecting relay circuits. Reference is made to the use of a magnetic disc or tape in place of a drum. Drum and head construction.-The drum 20, Fig. 1, is wound with cunife wire providing the required magnetic surface, and its shaft 21 is rotated by a motor (not shown) through a belt- and-pulley drive. The read-write heads 28, one for each of the 78 tracks (2 space), are mounted in staggered formation in a drum housing 31. Each head, Fig. 2, comprises a laminated core 30 on which the read and write coils 29 are mounted, and a terminal plug with prongs 34, this assembly being mounted by an adjustment nut 33 in a block 32. The gap between the drum 20 and head 28 is between 0.5 and 2 mils. Read operation.-The Read Drum Select Instruction will cause line 95, Fig. 32c, and one of the lines 94a-94d, corresponding to the required drum, to be marked with positive potentials, thus priming AND gates 142 and 155, Figs. 32c and 32a, through gates 139, 136 and 138 and lines 141, 141a, and operating drum selector and relay switching circuits whereby the reading heads SH, IH, Fig. 32d, associated with the sync and index tracks for the required drum are connected to pulse-amplifying and shaping circuits 187, 188 and 173, 174, the index pulse being also lengthened in single shot multivibrator 176. The timing and index pulses thus obtained are applied to lines 135, 130 respectively, Figs. 32d and 32a. The Set Drum Instruction primes gates 86, 88 through line 86a, whereby at fixed times during the " Execute-Regenerate " portion of the main machine cycle, pulses will be applied through gate 61 and inverter 62 to line 64 and through inverter 91 to line 58. The pulse on 64 is applied to the drum counter 35-45, Fig. 32b, assumed to be reset to zero; the connections, through cathode followers, between successive triggers are such that the counter acts subtractively so that this pulse will set all the triggers to " I." The pulse on 58 is applied to gates 47-57 connecting the counter triggers to corresponding triggers in the address register, to cause a switching to " 0 of those counter triggers for which " 0 is registered in the corresponding address triggers. If no Set Drum signal is provided, the number in the address register will not be transferred to the drum counter, and the zero address will be selected. The Copy Instruction provides a signal on line 148, Fig. 32c, which passes through the gate 142 and, after a delay determined by single-shot multivibrator 145, sets a trigger circuit 147 which in turn sets a trigger circuit 151. The resultant positive potential on line 153 is applied to gate 155, Fig. 32a, to allow the next index pulse on 130 to set trigger 160; the resultant positive potential on line 123 allows the timing pulses on 135 to pass through gate 134 (which gate is, however, inhibited through inverter 131 by the index pulse) to gate 61 and the drum counter input line 64. When the counter is stepped to zero, carry pulses will be obtained from AND circuits 65 and 67, Fig. 32b, which pulses are applied to AND gate 72 to produce a " true end carry pulse on line 78 which is passed through gate 79 (opened by the positive potentials on lines 123, 153) to set a trigger 83 which opens a gate 73, and is also passed through gate 80 to line 82a, Figs. 32b and 32c. The positive potentials on lines 95 (read drum select), 123 and 124 (" copy " trigger 147), allow this pulse to control gates 122, 355a, and a pulselengthening multivibrator 356, to produce a " drum read gate " signal (C, Fig. 5e) on line 126, Figs. 32c and 32d. This allows a timing pulse (A, Fig. 5e) delayed in electromagnetic delay line 196 (B, Fig. 5e) to pass from line 198a through gate 205 (D, Fig. 5e) and trigger a multivibrator 207 whose output (E, Fig. 5e) controls a " peaker " 208 which produces a drum read sample pulse (F, Fig. 5e) applied to gates such as 215, one for each of the 36 storage tracks. The drum selector circuits cause the read coils for the storage tracks of the required drum to be connected via amplifiers such as 224a and squaring inverters such as 225 to the gates such as 215, so that if a " 1 " is read from any of the tracks the squared and inverted amplifier output (G and H, Fig. 5e) will permit the sample pulse to pass through the corresponding gate and set a trigger such as 226 (J and K, Fig. 5e). These triggers form a drum register for temporarily storing the binary number read from the selected drum. Accompanying the signal on line 126, Figs. 32c and 32d, is a signal on line 126a which, through gate 294 and line 296, initiates the following operations controlled by sequentially operated singleshot multivibrators 297, 301, 303:-the resetting of " copy " trigger 147 via line 299; the production of a signal on line 305a which is sent via gate 306 and line 308 to the main machine to control an MQ register (not shown); the resetting of the drum register via lines such as 312 whereby signals are applied to input/output lines 228 to transfer the read number to the MQ register; and the production of a " drum copy proceed signal on line 313 which permits a further " copy " signal to be sent to line 148, if required. If such a signal is sent, trigger 147 is again set and when a " middle carry " is obtained from circuit 65, Fig. 32b, it is passed through gates 73 and 80 to line 82a to produce a further drum read gate signal on line 126, Fig. 32c, to cause a further number to be read from the drum. Reading continues in this manner, once for every 128 pulses applied to the drum counter, until a " copy " signal is no longer provided when the carry pulse on line 82a will control gates 355a, 354 and multivibrator 356 so as to produce a reset signal on line 360 which is passed to line 59, Fig. 32b, to reset the drum counter and trigger 83, and to line 162 to reset trigger 151, Fig. 32c, which in turn resets trigger 160, Fig. 32a. The reset signal is sent also as a " drum disconnect " signal, Fig. 32d, to the Main Machine. Write Operation.-This is similar to the read operation except that the Write Drum Select Instruction will produce a positive potential on line 105, Fig. 32c, in place of 95, so as to render gate 127 operative in place of 122. A drum counter carry pulse will therefore produce a " drum write gate " signal on line 129 which allows a delayed timing pulse on the line 198a, Fig. 32d, to.pass throu