公开(公告)号：DE1935258A1

公开(公告)日：1971-01-14

申请号：DE1935258

申请日：1969-07-11

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER ,  REICHL LEOPOLD ,  EDWIN VOGT DIPL-ING DR ,  PAINKE HELMUT

IPC: G06F9/46 ,  G06F9/48

公开(公告)号：DE1938912A1

公开(公告)日：1971-02-11

申请号：DE1938912

申请日：1969-07-31

Applicant: IBM DEUTSCHLAND

Inventor： PETAR SKUIN DIPL-ING ,  GUENTER KELLER DIPL-ING ,  KNAUFT GUENTER ,  EDWIN VOGT DIPL-ING DR

IPC: G06F7/38 ,  G06F7/00 ,  G06F7/499 ,  G06F7/508 ,  G06F11/10 ,  H03K19/00

Abstract: In an arithmetic and logical unit suitable for "Adding," "AND," "OR" and "Exclusive OR" operations, additions are performed to the carry-dependent sum formation principle, while during the execution of logical operations, operand bit parity functions related to the respective operation are generated by means of a function generator. In an operation-dependent checking circuit the carries of additions or the parity functions of logical operations are combined for result parity prediction independently of the sum formed. For error-checking the result, the parity of the result bits is compared for compliance with the predicted parity.