公开(公告)号：DE2135592A1

公开(公告)日：1973-02-01

申请号：DE2135592

申请日：1971-07-16

Applicant: IBM DEUTSCHLAND

Inventor： GENG HELLMUTH R ,  HAJDU JOHANN ,  GOETZE VOLKMAR ,  SKUIN PETAR

IPC: G06F11/10 ,  H03M13/05

公开(公告)号：DE2134816A1

公开(公告)日：1973-02-01

申请号：DE2134816

申请日：1971-07-13

Applicant: IBM DEUTSCHLAND

Inventor： BOGER KLAUS ,  GOETZE VOLKMAR ,  GENG HELLMUTH R ,  HAJDU JOHANN

IPC: G06F12/10 ,  G06F13/06

Abstract: In a microprogrammed processor, a pair of register means and an associative store are arranged to eliminate the need to translate, for each microinstruction, a logical address to a real address to access main storage. Translation is required only once for each program or machine level (macro) instruction. The real addresses of the first bytes of the current instruction and its operand(s) are stored in a first one of the register means and are normally incremented to access the remainder of the instruction and operands byte-by-byte. In addition, the first register means and incrementer can be used to access sequentially stored instructions in a program sequence without address translation. When a page boundary is crossed during said incrementing, the logical page address of the current instruction or operand (which is at the boundary) is read from the second register means and is incremented to form the logical address of the next sequential page. This new logical address is searched in the associative array. If a match occurs, the new logical address is stored in the second register means, and the corresponding real address is stored in the first register means. This hardware translate means significantly reduces translate time.