Patent search ap:("IBM DEUTSCHLAND") AND inv:"HALLER WILHELM E" Page 1

1.

发明专利
未知

公开(公告)号：DE10225862B4

公开(公告)日：2009-12-17

申请号：DE10225862

申请日：2002-06-11

Applicant: IBM DEUTSCHLAND

Inventor： HALLER WILHELM E , SAUTTER ROLF , WENDEL DIETER , WETTER HOLGER

IPC: G06F7/50 , G06F7/506 , G06F7/507 , G06F9/30

2.

发明专利
Transfer network for addition of two bit groups such that circuit performance is enhanced and adding speed improved by use of a redundant logic circuit solely comprising NAND gates and inverters 未知

公开(公告)号：DE10225862A1

公开(公告)日：2003-01-30

申请号：DE10225862

申请日：2002-06-11

Applicant: IBM DEUTSCHLAND

Inventor： HALLER WILHELM E , SAUTTER ROLF , WENDEL DIETER , WETTER HOLGER

IPC: G06F7/506 , G06F7/507 , G06F9/30

Abstract: Method for generating a transfer signal (cy) from a transfer network (2) that is for adding two bit groups together (A, B) in an adder circuit, whereby the transfer network is implemented as a static hardware circuit. The circuit is based on a redundant logic circuit comprised solely of NAND gates (AI) and inverters (I). A further transfer path does not have inverters.

Patent Agency Ranking