公开(公告)号：DE3121562A1

公开(公告)日：1983-01-05

申请号：DE3121562

申请日：1981-05-30

Applicant: IBM DEUTSCHLAND

Inventor： GOETZE VOLKMAR ,  POTZ GUENTHER

IPC: G11C17/00 ,  H03K19/177

Abstract: A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array positions not being used for performing the respective PLA functions, control circuits are provided preceding the AND array as well as between the AND and the OR array. This allows an increase in the number of possible PLA functions to be performed by a given PLA thus providing PLA's with improved functional density. The control circuits essentially consist of two-stage AND-OR circuits being fully compatible with the AND and OR array technology of the PLA. For optimum utilization of the Don't Care positions and planes, each functional input can be switched to any discretionary functional line of the PLA. By providing an additional control line in the OR array, the control logic for the entire OR array is reduced to only two AND gates.