公开(公告)号：DE2131787A1

公开(公告)日：1973-01-11

申请号：DE2131787

申请日：1971-06-26

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  SKUIN PETAR ,  VOGT EDWIN DR ,  ROLAND GENG HELLMUTH

IPC: G06F11/08 ,  G06F11/10 ,  H04L1/00 ,  H03K13/32

Abstract: In a data processing system, a first processing unit is connected to several other processing units by one transfer bus each for the two directions of transmission, a circuit arrangement for error detection being associated with the transfer lines. The first unit comprises a check character generator generating a parity check character both for the information to be transferred from the first processing unit to the further processing units and from the further processing units to the first processing unit. The transfer lines of both directions are provided with a common transfer path, by means of which the parity check characters generated by the check character generator are transferred from the first unit to the further units. Each of the further units comprises a check circuit connected to the two transfer buses and the check character transfer path and checking the correctness of the transferred information for both directions of transmission.