公开(公告)号：DE2725613A1

公开(公告)日：1977-12-29

申请号：DE2725613

申请日：1977-06-07

Applicant: IBM DEUTSCHLAND

Inventor： MIERSCH EKKEHARD FRITZ DIPL PH ,  SPAMPINATO DOMINIC PATRICK

IPC: G11C11/405 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/24

Abstract: 1523094 Transistor memory cells INTERNATIONAL BUSINESS MACHINES CORP 25 April 1977 [17 June 1976] 17190/77 Heading H3T A memory cell comprises a single storage capacitor C, coupled in a series circuit including the source-drain paths of two FET's 1, 3 between two bit/sense lines B/S0, B/S1, the gate electrodes of the two transistors being coupled to the word line. The cell provides a differential signal and obviates the need for a dummy cell to provide a reference signal for detecting the cell state. To write data into the cell, the transistors 1,3 are turned on to allow capacitor C s to charge in one sense or the other, depending on whether a "0" or a " 1" is being written in. The transistors are then turned off to leave the capacitor floating. To read, the transistors are again turned on, and the differential voltage across the capacitor is sensed between the bit/sense lines.