公开(公告)号：FR1504609A

公开(公告)日：1967-12-08

申请号：FR06008054

申请日：1966-09-21

Applicant: IBM FRANCE

Inventor： PIERRET JEAN MARC

IPC: H04L25/48 ,  H04L25/497

Abstract: 1,154,648. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 5 Sept., 1967 [21 Sept., 1966], No. 40619/67. Heading H4P. Each bit of data to be transmitted is encoded as a main pulse followed and preceded by several "echo" pulses of lower amplitude than the main pulse, the encoding being such that no main pulse coincides with any echo pulse. In the system described each input bit of duration T, Fig. 2 (part shown), produces a main pulse A of duration T/2, two echo pulses a1, a 1 1 of opposite polarity to pulse A, and two smaller echoes a3, a 1 3 of the same polarity, the echo pulses being spaced as shown and having a duration T/2. An input bit of opposite state produces the inverse signal. The transmitted signal is the sum of the encoded bits. The encoder, Fig. 3a (not shown), comprises a shift register fed by the input bits and giving a parallel output. The final stage of the register controls a switched potential divider which passes a pulse representing the main pulse to a first gate. The echo pulses appear at the output of a second gate, one input of which is obtained from a potential divider fed by the outputs of switched dividers controlled by other stages of the register. The gates are enabled alternately for a period T which is 90 degrees out of phase with the input bits. Thus the gates respectively pass two main pulses or two echo pulses when enabled. The gates' outputs pass via an OR gate to the transmitter. At the receiver the original data is recovered by sampling the received signal at times 2nT and 2nt + T/2.