公开(公告)号：JPH02238553A

公开(公告)日：1990-09-20

申请号：JP5776289

申请日：1989-03-13

Applicant: IBM JAPAN

Inventor： FUKUDA MUNEHIRO ,  MATSUMOTO TAKASHI ,  NAKADA TAKEO

IPC: G06F15/173 ,  G06F9/45 ,  G06F9/52 ,  G06F15/167

Abstract: PURPOSE:To ensure the effective use of a multiprocessor system for plural applications by transmitting the synchronism satisfaction signals to the corresponding processors based on the result of the comparison carried out between the signal received from a synchronizing signal bus and the contents of a synchronous register. CONSTITUTION:The synchronizing signal lines SL1 - SLn of a synchronizing signal bus 2 are assigned to the processors P1 - Pn respectively. Then the syn chronizing signals Sync are transmitted from the processors P1 - Pn. A compara tor 4 samples the data on the bus 2 for each clock or each half clock and compares them with the data on a synchronous register 3. A timing control circuit 5 receives the signals Sync and returns the signals Sync and Ack accord ing to the clocks. Thus it is possible to attain at a high speed many synchronous states among the processes to which the processors P1 - Pn are assigned and to carry out plural parallel processing programs at the same time.