公开(公告)号：JPH02297647A

公开(公告)日：1990-12-10

申请号：JP11728289

申请日：1989-05-12

Applicant: IBM JAPAN

Inventor： INAZUMI JUNICHI ,  KOBAYASHI SHIGETAKA ,  NAKAMOTO ATSUSHI

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00

Abstract: PURPOSE:To increase a usable memory space by providing a means to control a multiplexer so as to exchange a row address signal and a column address signal and to generate a signal with responding to an address switching signal. CONSTITUTION:By responding to a selecting signal supplied from a controller 1, a multiplexer 4 selectively supplies high-order 10 bits and low-order 10 bits out of the address signal of 20 bits to an address decoder 7. The address decoder 7 supplies this signal respectively to a row address line driver 8 and a column address line driver 9. Accordingly, the address signal of 20 bits sent from the controller 1 is controlled by the selecting signal and can address an arbitrary location in a memory 2 as the row address signal of 10 bits and the column address signal of 10 bits. Thus, the capacity of a usable block without error is increased.