公开(公告)号：JPH09160723A

公开(公告)日：1997-06-20

申请号：JP31779795

申请日：1995-12-06

Applicant: IBM JAPAN

Inventor： MUNETO SEIJI ,  NIIJIMA HIDETO ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10

Abstract: PROBLEM TO BE SOLVED: To prevent a data storage system from being complicated by transferring fast the data via data buses and also facilitating the control of the timing of the system. SOLUTION: The mutual synchronization of accesses is secured among storage means 13 to 17 which store the data. For this purpose, the data buses 11 and 12 are prepared to transfer the data together with an input/output means 21 which transfers the plural data series to the buses 11 and 12 with interleave, and a latch means 23 which is provided at plural stages and in series between the means 13 to 17 and the buses 11 and 12 and hold the data respectively.

公开(公告)号：JPH08202497A

公开(公告)日：1996-08-09

申请号：JP1043595

申请日：1995-01-26

Applicant: IBM JAPAN

Inventor： MUNETO SEIJI ,  NIIJIMA HIDETO ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16

Abstract: PURPOSE: To facilitate transfer operation and restore data efficiently at a high speed in the case of fault occurrence by providing plural storage means, a data bus, and a selecting means having a function for parity arithmetic operation. CONSTITUTION: Two channels of 4-channel crossbar switches 11a and 11b having an exclusive OR operation function are connected to data buses DDO and DD1 as common buses. Other two channels of the crossbar switch 11a as the selecting means are connected to drives HDDO and HDD1. Other two channels of the crossbar switch 11b are connected to drives HDD2 and HDD3. Further, the crossbar switches 11a and 11b are controlled with an address signal and a control signal outputted from a data bus controller 13, and connections in optional combinations of drives and data buses are enabled. Thus, the selecting means itself is provided with the function for parity arithmetic operation.

公开(公告)号：JPH086736A

公开(公告)日：1996-01-12

申请号：JP13468694

申请日：1994-06-16

Applicant: IBM JAPAN

Inventor： NIIJIMA HIDETO ,  MUNETO SEIJI ,  MURATA HIROKI ,  TAKAHASHI NOBUAKI

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  G06F11/18 ,  G06F11/20

Abstract: PURPOSE:To write and read data fast through simple constitution. CONSTITUTION:This disk storage device is equipped with two data buses 100 and 200 for data transfer and an HDD 0 and an HDD 1 are connected fixedly to the data buses 100 and 200, respectively, and an MCU 32 outputs a specific signal to a DPC 10 according to a command from a host, and then multiplexers 20 and 22 connect the HDD 2 and HDD 3 to either of the data buses 100 and 200. Thus, the HDD 2 and HDD 3 are connected to one of the data buses 100 and 200 and data are written on and read out of HDDs 0-3.