公开(公告)号：JPH02186456A

公开(公告)日：1990-07-20

申请号：JP479989

申请日：1989-01-13

Applicant: IBM JAPAN

Inventor： MORIWAKI ATSUSHI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: PURPOSE:To flexibly switch by receiving a request signal and a write address to be sent, executing data operation corresponding to the type of its own data consistency maintaining procedure, which can be arbitrarily set, and returning data to a private cache. CONSTITUTION:When writing is executed to the 'shared' data of a private cache 2a, the request signal and update data are sent to a common bus 4 and after that, a response signal is waited. Controllers 3b and 3c of other caches 2b and 2c recognize the request signal and change data on the bus 4 respectively and execute determined operation to modification mode registers 8b and 8c. In the cache 2b side, the register 8b is positive and the controller 3b returns a negative signal as the response signal. On the other hand, in the cache 2c side, the register 8c is negative. Then, when the cache 2c obtains the data of the same address, the controller 3c updates these data by the update data and returns a positive signal as the response signal or otherwise, the controller 3c only returns the negative signal as the response signal. When the positive response signal is returned, the data are 'shared' in the cache 2a and when the negative response signal is returned, the data are 'occupied'.