公开(公告)号：EP2953265B1

公开(公告)日：2016-12-14

申请号：EP14171580.5

申请日：2014-06-06

Applicant: IMEC VZW

Inventor： Deguchi, Kazuaki ,  Verbruggen, Bob ,  Craninckx, Jan

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/14 ,  H03M1/468 ,  H03M2201/4233

公开(公告)号：EP2107683A1

公开(公告)日：2009-10-07

申请号：EP08075253.8

申请日：2008-03-31

Applicant: IMEC

Inventor： Van der Plas, Geert ,  Verbruggen, Bob

IPC: H03M1/36 ,  H03M1/42

CPC classification number: H03M1/125 ,  H03M1/002 ,  H03M1/1235 ,  H03M1/361 ,  H03M1/42

Abstract: The present invention is related to an analog-to-digital converter circuit (1) wherein a comparator based asynchronous binary search is used. The architecture comprises a self-clocked (asynchronous) binary tree of comparators, each having a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator (2) only, preferably to the first or root comparator. The at least one comparator (2) is further arranged for controlling at least one other comparator (3) of the plurality of comparators (2, 3, 4).

Abstract translation: 本发明涉及一种使用基于比较器的异步二进制搜索的模拟 - 数字转换器电路（1）。 该架构包括每个具有预定阈值的比较器的自定时（异步）二进制树。 输入信号与闪存转换器的情况并行地应用于所有比较器，但是时钟仅施加到（至少）一个比较器（2），优选地应用于第一或根比较器。 所述至少一个比较器（2）还被布置用于控制所述多个比较器（2,3,4）中的至少一个其它比较器（3）。

公开(公告)号：EP2629429B1

公开(公告)日：2016-10-19

申请号：EP13153377.0

申请日：2013-01-31

Applicant: IMEC ,  Renesas Electronics Corporation

Inventor： Verbruggen, Bob ,  Iriguchi, Masao ,  Craninckx, Jan

IPC: H03M1/10 ,  H03M1/14 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03M1/1023 ,  H03M1/145 ,  H03M1/466

公开(公告)号：EP2629429A1

公开(公告)日：2013-08-21

申请号：EP13153377.0

申请日：2013-01-31

Applicant: IMEC ,  Renesas Electronics Corporation

Inventor： Verbruggen, Bob ,  Iriguchi, Masao ,  Craninckx, Jan

IPC: H03M1/10

CPC classification number: H03M1/06 ,  H03M1/1023 ,  H03M1/145 ,  H03M1/466

Abstract: The present invention relates to an analogue-to-digital converter (1) for converting an input voltage signal into a digital output signal representing said input voltage signal. The analogue-to-digital converter comprises
sampling means (3) for sampling the input voltage signal (2),
one or more comparators (5) arranged for receiving the sampled input voltage signal,
a digital-to-analogue converter (7), DAC, comprising circuitry adapted for generating a search signal approximating said input voltage signal and a calibration signal, said search signal and said calibration signal to be applied to a comparator of said one or more comparators,
a search logic block (10) arranged for receiving a comparator output signal from the one or more comparators, for providing input to the DAC (7) for generating said search signal, and for producing a digital output signal,
calibration logic block (9) adapted for producing a control signal to control said circuitry of the DAC and comprising processing means for observing the digital output signal, for comparing the digital output signal with a desired output and for compensating analogue non-idealities
of the analogue-to-digital converter,
whereby the circuitry of the DAC is adapted for generating the calibration signal in accordance with the control signal and with the sampled input voltage signal.

Abstract translation: 本发明涉及一种用于将输入电压信号转换为表示所述输入电压信号的数字输出信号的模拟 - 数字转换器（1）。 模数转换器包括用于对输入电压信号（2）进行采样的采样装置（3），被布置用于接收采样的输入电压信号的一个或多个比较器（5），数模转换器（7）， DAC，包括适于产生近似所述输入电压信号的搜索信号和校准信号的电路，所述搜索信号和所述校准信号被施加到所述一个或多个比较器的比较器;搜索逻辑块（10），布置成用于接收 来自所述一个或多个比较器的比较器输出信号，用于向所述DAC（7）提供用于产生所述搜索信号的输入，以及用于产生数字输出信号，校准逻辑块（9）适于产生控制信号以控制所述电路 并且包括用于观察数字输出信号的处理装置，用于将数字输出信号与期望的输出进行比较，并用于补偿模数转换器的模数非理想 其中DAC的电路适于根据控制信号和采样的输入电压信号产生校准信号。

公开(公告)号：EP2977989B1

公开(公告)日：2019-05-08

申请号：EP14178665.7

申请日：2014-07-25

Applicant: IMEC VZW

Inventor： Verbruggen, Bob ,  Deguchi, Kazuaki ,  Craninckx, Jan

IPC: G11C27/02 ,  H03M1/12

公开(公告)号：EP2977989A1

公开(公告)日：2016-01-27

申请号：EP14178665.7

申请日：2014-07-25

Applicant: IMEC VZW

Inventor： Verbruggen, Bob ,  Deguchi, Kazuaki ,  Craninckx, Jan

IPC: G11C27/02

CPC classification number: G11C27/02 ,  H03M1/1245

Abstract: The present invention relates to a sample-and-hold circuit (1) comprising
- a transistor (11) arranged for switching between a sample mode and a hold mode,
- a bootstrap circuit (2) arranged for maintaining in said sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in said hold mode, said bootstrap circuit comprising a bootstrap capacitance (21) arranged for being precharged to a given voltage during said hold mode, said bootstrap capacitance being connected between the source terminal and the gate terminal during said sample mode, characterised in that the bootstrap circuit comprises a switched capacitor charge pump (22) for generating that given voltage.

Abstract translation: 本发明涉及一种采样和保持电路（1），包括：晶体管（11），布置成用于在采样模式和保持模式之间切换; - 自举电路（2），布置成用于在所述采样模式中保持电压 源极端子和晶体管的栅极端子之间的电平，独立于源极端子处的电压并被布置为在所述保持模式下关断晶体管，所述自举电路包括布置成预充电到给定电压的自举电容（21） 在所述保持模式期间，所述自举电容在所述采样模式期间连接在所述源极端子和所述栅极端子之间，其特征在于，所述自举电路包括用于产生所述给定电压的开关电容器电荷泵（22）。

公开(公告)号：EP2953265A1

公开(公告)日：2015-12-09

申请号：EP14171580.5

申请日：2014-06-06

Applicant: IMEC VZW

Inventor： Deguchi, Kazuaki ,  Verbruggen, Bob ,  Craninckx, Jan

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/14 ,  H03M1/468 ,  H03M2201/4233

Abstract: The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising
- precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V ref ) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors,
- setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff ) at said first terminals,
- applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal,
- quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel,
- comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch.

公开(公告)号：EP2546992B1

公开(公告)日：2014-03-05

申请号：EP11173743.3

申请日：2011-07-13

Applicant: IMEC

Inventor： Verbruggen, Bob ,  Craninckx, Jan

IPC: H03M1/04 ,  H03M1/20 ,  H03M1/16 ,  H03M1/44 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/04 ,  H03M1/164 ,  H03M1/44 ,  H03M1/46

公开(公告)号：EP2629428A1

公开(公告)日：2013-08-21

申请号：EP12155784.7

申请日：2012-02-16

Applicant: IMEC ,  Renesas Electronics Corporation

Inventor： Verbruggen, Bob ,  Iriguchi, Masao ,  Craninckx, Jan

IPC: H03M1/10

CPC classification number: H03M1/06 ,  H03M1/1023 ,  H03M1/145 ,  H03M1/466

Abstract: The present invention relates to an analogue-to-digital converter (1) for converting an input voltage signal into a digital code representing said input voltage signal. The analogue-to-digital converter comprises
sampling means (3) for sampling the input voltage signal (2),
one or more comparators (5),
a digital-to-analogue converter (7), DAC, comprising circuitry for generating a calibration signal to be applied to a comparator of said one or more comparators and
calibration logic block (9) adapted for producing a control signal to control said circuitry and
comprising processing means for observing the analogue-to-digital converter's output and for
comparing said output with a desired output,

whereby the circuitry of the DAC is adapted for generating the calibration signal in accordance with the control signal and with the sampled input voltage signal.

Abstract translation: 本发明涉及一种用于将输入电压信号转换成表示所述输入电压信号的数字码的模拟 - 数字转换器（1）。 模数转换器包括用于对输入电压信号（2）进行采样的采样装置（3），一个或多个比较器（5），数模转换器（7），DAC，包括用于产生校准 信号加到所述一个或多个比较器和校准逻辑块（9）的比较器，校准逻辑块（9）适于产生控制信号以控制所述电路，并包括处理装置，用于观察模拟 - 数字转换器的输出并将所述输出与 期望的输出，由此DAC的电路适于根据控制信号和采样的输入电压信号来生成校准信号。

公开(公告)号：EP2546992A1

公开(公告)日：2013-01-16

申请号：EP11173743.3

申请日：2011-07-13

Applicant: IMEC

Inventor： Verbruggen, Bob ,  Craninckx, Jan

IPC: H03M1/04 ,  H03M1/20 ,  H03M1/16 ,  H03M1/44 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/04 ,  H03M1/164 ,  H03M1/44 ,  H03M1/46

Abstract: The present invention is related to an analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal (1) and for outputting a digital representation (6) of said analog input signal (1). The A/D converter circuit comprises:
- a first converter stage (2) configured for receiving the analog input signal (1) and for generating a first set (3) of conversion bits, a first completion signal (7) and a residual analog output signal (4) representing the difference between the analog input signal and a signal represented by said first set of conversion bits,
- a second converter stage (5) comprising
o a clock generation circuit (8) arranged for receiving the first completion signal and for generating a clock signal,
o a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions,
o a digital processing stage (9) configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits,

- means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.

Abstract translation: 本发明涉及一种被配置用于接收模拟输入信号（1）并用于输出所述模拟输入信号（1）的数字表示（6）的模拟（A / D）转换器电路。 A / D转换器电路包括： - 第一转换器级（2），被配置为接收模拟输入信号（1）并产生第一组（3）转换位，第一完成信号（7）和残余模拟 输出信号（4），其表示模拟输入信号和由所述第一组转换位表示的信号之间的差; - 第二转换器级（5），包括被设置用于接收第一完成信号的时钟产生电路（8） 生成时钟信号，多个比较器被配置为用于接收残余模拟输出信号和公共参考电压，所述多个比较器被布置成被时钟信号激活并用于输出多个比较器判定，数字处理阶段 （9），被配置为用于接收所述多个比较器判定并用于生成第二组转换位; - 用于生成所述转换位的数字表示的装置 模拟输入信号通过组合第一和第二组转换位。