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公开(公告)号：US20160027528A1
公开(公告)日：2016-01-28
申请号：US14808267
申请日：2015-07-24
Applicant: IMEC VZW
Inventor： Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
CPC classification number: G11C27/02 , H03M1/1245
Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
Abstract translation: 本公开涉及一种采样和保持电路，包括：晶体管，被布置用于在采样模式和保持模式之间切换;以及自举电路，布置成用于在采样模式中保持源极端子和栅极端子之间的电压电平 晶体管与源极端子处的电压无关，并且被设置为在保持模式下关断晶体管。 引导电路包括自举电容，其布置成在保持模式期间被预充电到给定电压，自举电容在采样模式期间连接在源极端子和栅极端子之间。 在一个示例中，自举电路包括用于产生给定电压的开关电容器电荷泵。
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2.发明授权公开(公告)号：US09166608B1
公开(公告)日：2015-10-20
申请号：US14731471
申请日：2015-06-05
Applicant: IMEC VZW
Inventor： Kazuaki Deguchi , Bob Verbruggen , Jan Craninckx
CPC classification number: H03M1/0604 , H03M1/00 , H03M1/002 , H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/1215 , H03M1/14 , H03M1/468 , H03M2201/4233
Abstract: Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.
Abstract translation: 这里的方法和装置涉及用于估计时间交织的A / D转换器中的带宽不匹配的方法。 示例性方法包括：在多个通道的每个通道中将电容器的端子预充电到第一状态，并对通过第一可切换路径施加的参考模拟输入电压信号（Vref）进行采样，由此在第一端子处接收采样的输入电压信号 电容器 该方法还包括将每个信道的第二终端设置为第二状态。 该方法还包括经由第二可切换路径将参考模拟输入电压信号施加到第一端子，从而在第一端子上产生非零稳定误差。 该方法另外包括量化沉降误差以获得非零建立误差的估计。 该方法还包括比较非零建立误差的估计并导出带宽不匹配的估计。
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公开(公告)号：US09349484B2
公开(公告)日：2016-05-24
申请号：US14808267
申请日：2015-07-24
Applicant: IMEC VZW
Inventor： Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
CPC classification number: G11C27/02 , H03M1/1245
Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
Abstract translation: 本公开涉及一种采样和保持电路，包括：晶体管，被布置用于在采样模式和保持模式之间切换;以及自举电路，布置成用于在采样模式中保持源极端子和栅极端子之间的电压电平 晶体管与源极端子处的电压无关，并且被设置为在保持模式下关断晶体管。 引导电路包括自举电容，其布置成在保持模式期间被预充电到给定电压，自举电容在采样模式期间连接在源极端子和栅极端子之间。 在一个示例中，自举电路包括用于产生给定电压的开关电容器电荷泵。
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