公开(公告)号：US10354868B2

公开(公告)日：2019-07-16

申请号：US15819226

申请日：2017-11-21

Applicant: IMEC VZW

Inventor： Salim El Kazzi ,  Clement Merckling

IPC: C23C14/30 ,  H01L21/02 ,  C30B23/02 ,  C30B23/06 ,  C30B29/46 ,  H01L21/687 ,  C23C14/00 ,  C23C14/06 ,  C23C14/54 ,  C30B23/00 ,  H01L21/67

Abstract: A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.

公开(公告)号：US20180183212A1

公开(公告)日：2018-06-28

申请号：US15840779

申请日：2017-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D ,  Universiteit Gent

Inventor： Joris Van Campenhout ,  Clement Merckling ,  Maria Ioanna Pantouvaki ,  Ashwyn Srinivasan ,  Irina Kulkova

IPC: H01S5/323 ,  H01S5/026 ,  H01S5/30 ,  H01S5/042

Abstract: An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled. The waveguide is optically coupled to passive waveguides at either end thereof. The fin structure includes an array of fin elements, each fin element comprising Group III-V materials.

公开(公告)号：US09947591B2

公开(公告)日：2018-04-17

申请号：US15352960

申请日：2016-11-16

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Guillaume Boccardi

IPC: H01L21/8238 ,  H01L27/06 ,  H01L21/8258 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/02543 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US20180082907A1

公开(公告)日：2018-03-22

申请号：US15825826

申请日：2017-11-29

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Guillaume Boccardi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/823807 ,  H01L21/02543 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US20160141391A1

公开(公告)日：2016-05-19

申请号：US14938169

申请日：2015-11-11

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/41725 ,  H01L29/7848

Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Abstract translation: 提供了一种在SinGe1-n衬底上生长III-V半导体结构的方法，其中n为0至1。 该方法包括以下步骤：（a）使SinGe1-n衬底达到高温; （b）将载体气体中的V族前体暴露于5〜30分钟，由此在该区域形成掺杂区域; （c）使SinGe1-n基板处于低温; （d）将载体气体中的掺杂区域暴露于III族前体，并在载气中暴露于V族前体，直至在成核层上形成5〜15nm的III-V材料的成核层; （e）使SinGe1-n基板达到中间温度; 和（f）将成核层暴露于载气中的III族前体和载气中的V族前体。

公开(公告)号：US10763643B2

公开(公告)日：2020-09-01

申请号：US15840779

申请日：2017-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D ,  Universiteit Gent

Inventor： Joris Van Campenhout ,  Clement Merckling ,  Maria Ioanna Pantouvaki ,  Ashwyn Srinivasan ,  Irina Kulkova

IPC: H01S5/323 ,  H01S5/026 ,  H01S5/042 ,  H01S5/10 ,  H01S5/343 ,  H01S5/12 ,  H01S5/02 ,  H01S5/30

Abstract: An electrically-operated semiconductor laser device and method for forming the laser device are provided. The laser device includes a fin structure to which a waveguide is optically coupled. The waveguide is optically coupled to passive waveguides at either end thereof. The fin structure includes an array of fin elements, each fin element comprising Group III-V materials.

公开(公告)号：US20190214474A1

公开(公告)日：2019-07-11

申请号：US16222911

申请日：2018-12-17

Applicant: IMEC vzw

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L29/43 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  G06N10/00

CPC classification number: H01L29/437 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/28264 ,  H01L21/28575 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/32058 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

公开(公告)号：US09419110B2

公开(公告)日：2016-08-16

申请号：US14938169

申请日：2015-11-11

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/41725 ,  H01L29/7848

Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Abstract translation: 提供了一种在SinGe1-n衬底上生长III-V半导体结构的方法，其中n为0至1。 该方法包括以下步骤：（a）使SinGe1-n衬底达到高温; （b）将载体气体中的V族前体暴露于5〜30分钟，由此在该区域形成掺杂区域; （c）使SinGe1-n基板处于低温; （d）将载体气体中的掺杂区域暴露于III族前体，并在载气中暴露于V族前体，直至在成核层上形成5〜15nm的III-V材料的成核层; （e）使SinGe1-n基板达到中间温度; 和（f）将成核层暴露于载气中的III族前体和载气中的V族前体。

公开(公告)号：US20150333122A1

公开(公告)日：2015-11-19

申请号：US14715041

申请日：2015-05-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/20 ,  H01L29/34 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02538 ,  H01L21/02603 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/34 ,  H01L29/413 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/78681

Abstract: An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.

Abstract translation: 示例性半导体结构包括第一表面和至少一个纳米线，所述至少一个纳米线垂直于所述第一表面，其中所述第一表面是缺陷差的并且由掺杂的III-V半导体材料制成，其中所述至少一个 一个纳米线是缺陷缺陷的，并且由与第一表面的材料具有约0％至1％的晶格失配的未掺杂的III-V半导体材料制成。

公开(公告)号：US20190181050A1

公开(公告)日：2019-06-13

申请号：US16280428

申请日：2019-02-20

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Guillaume Boccardi

IPC: H01L21/8238 ,  H01L29/786 ,  H01L21/8258 ,  H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L27/06 ,  H01L21/02

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.