公开(公告)号：US20210375615A1

公开(公告)日：2021-12-02

申请号：US17228295

申请日：2021-04-12

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mikhail Krishtab ,  Silvia Armini

IPC: H01L21/027

Abstract: In a first aspect, the present disclosure relates to a method for forming a patterning mask over a layer to be patterned, the method comprising: (a) providing a first layer over a substrate, the substrate comprising the layer to be patterned, the first layer being capable to bond with a monolayer comprising a compound comprising a functional group for bonding to the first layer and a removable organic group, (b) bonding the monolayer to the first layer, (c) exposing the monolayer to an energy beam, thereby forming a pattern comprising a first area comprising the compound with the removable organic group and a second area comprising the compound not having the removable organic group, and (d) selectively depositing an amorphous carbon layer on top of the first area.

公开(公告)号：US20190198391A1

公开(公告)日：2019-06-27

申请号：US16190921

申请日：2018-11-14

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mikhail Krishtab ,  Silvia Armini ,  Ivo Stassen ,  Rob Ameloot

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

Abstract: Example embodiments relate to selective deposition of metal-organic frameworks. One embodiment includes a method of forming a low-k dielectric film selectively on exposed dielectric locations in a substrate. The method includes selectively depositing a metal-containing film, using an area-selective deposition process, on the exposed dielectric locations using one or more deposition cycles. The method also includes providing, at least once, a vapor of at least one organic ligand to the deposited metal-containing film resulting in a gas-phase chemical reaction thereby obtaining a metal-organic framework which is the low-k dielectric film. The low-k dielectric film has gaps on locations where no metal-containing film was deposited.

公开(公告)号：US20250120088A1

公开(公告)日：2025-04-10

申请号：US18906994

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Sana Rachidi ,  Maarten Rosmeulen ,  Silvia Armini

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27

Abstract: The present disclosure relates to a method that includes forming a layer stack over a substrate; forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back inter-gate spacer layers of the layer stack; forming sacrificial layers in the first recessed areas; forming second recessed areas in the sidewall by laterally etching back gate layers of the layer stack; forming a lateral memory stack in each second recessed area by selectively depositing, in the second recessed areas, a blocking oxide and, subsequently, a charge trap material. The method further includes removing the sacrificial layers by etching from the memory hole; re-growing the inter-gate spacer layers such that the lateral memory stacks are vertically separated by the re-grown inter-gate spacer layers; forming a tunneling oxide layer in the memory hole; and forming a channel layer along the tunneling oxide layer.

公开(公告)号：US10790382B2

公开(公告)日：2020-09-29

申请号：US15845300

申请日：2017-12-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Silvia Armini ,  Elisabeth Camerotto ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/775 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

公开(公告)号：US20160268208A1

公开(公告)日：2016-09-15

申请号：US15067033

申请日：2016-03-10

Applicant: IMEC VZW

Inventor： Silvia Armini

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  C23C18/12 ,  C23C18/20 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76862 ,  H01L21/76874

Abstract: An electronic circuit structure comprising a substrate, a dielectric layer on top of the substrate and comprising a cavity having side-walls, a manganese or manganese nitride layer covering the side-walls, and a self-assembled monolayer, comprising an organic compound of formula Z-L-A, covering the manganese or manganese nitride layer, wherein Z is selected from the list consisting of a primary amino group, a carboxylic acid group, a thiol group, a selenol group and a heterocyclic group having an unsubstituted tertiary amine in the cycle, wherein L is an organic linker comprising from 1 to 12 carbon atoms and from 0 to 3 heteroatoms, and wherein A is a group attaching the linker to the manganese or manganese nitride layer.

Abstract translation: 一种电子电路结构，包括基底，位于基底顶部的电介质层，包括具有侧壁的空腔，覆盖侧壁的锰或氮化锰层，以及自组装单层，其包含式 ZLA，覆盖锰或氮化锰层，其中Z选自伯胺基，羧酸基，硫醇基，硒酚基和在该循环中具有未取代的叔胺的杂环基，其中 L是包含1至12个碳原子和0至3个杂原子的有机连接体，其中A是将连接体连接到锰或氮化锰层的基团。

公开(公告)号：US10090393B2

公开(公告)日：2018-10-02

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US20180182868A1

公开(公告)日：2018-06-28

申请号：US15845300

申请日：2017-12-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Silvia Armini ,  Elisabeth Camerotto ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

公开(公告)号：US20150091142A1

公开(公告)日：2015-04-02

申请号：US14488857

申请日：2014-09-17

Applicant: IMEC VZW

Inventor： Christoph Adelmann ,  Silvia Armini

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02318 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/02107 ,  H01L21/02112 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/02299 ,  H01L21/02304 ,  H01L29/06

Abstract: The present disclosure relates to a method (100) for depositing a layer on a III-V semiconductor substrate, in which this method comprises providing (102) a passivated III-V semiconductor substrate comprising a III-V semiconductor surface which has a surface passivation layer provided thereon for preventing oxidation of said III-V semiconductor surface. The surface passivation layer comprises a self-assembled monolayer material obtainable by the reaction on the surface of an organic compound of formula R-A, wherein A is selected from SH, SeH, TeH and SiX3. X is selected from H, Cl, O—CH3, O—C2H5, and O—C3H2, and R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms. The method further comprises thermally annealing (107) the III-V semiconductor substrate in a non-oxidizing environment such as to decompose the self-assembled monolayer material, and depositing (108) a layer on the III-V semiconductor surface in the non-oxidizing environment.

Abstract translation: 本公开涉及一种用于在III-V半导体衬底上沉积层的方法（100），其中该方法包括提供（102）钝化的III-V半导体衬底，其包括具有表面钝化的III-V半导体表面 层，用于防止所述III-V半导体表面的氧化。 表面钝化层包括通过在式R-A的有机化合物的表面上的反应获得的自组装单层材料，其中A选自SH，SeH，TeH和SiX 3。 X选自H，Cl，O-CH 3，O-C 2 H 5和O-C 3 H 2，R是包含5至20个碳原子的烃基，氟代碳基或氢氟碳基。 该方法还包括在非氧化环境中对III-V半导体衬底进行热退火（107），以分解自组装单层材料，以及在非绝缘层中的III-V半导体表面上沉积（108） 氧化环境。

公开(公告)号：US11923198B2

公开(公告)日：2024-03-05

申请号：US17228295

申请日：2021-04-12

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mikhail Krishtab ,  Silvia Armini

IPC: H01L21/027

CPC classification number: H01L21/0273

Abstract: In a first aspect, the present disclosure relates to a method for forming a patterning mask over a layer to be patterned, the method comprising: (a) providing a first layer over a substrate, the substrate comprising the layer to be patterned, the first layer being capable to bond with a monolayer comprising a compound comprising a functional group for bonding to the first layer and a removable organic group, (b) bonding the monolayer to the first layer, (c) exposing the monolayer to an energy beam, thereby forming a pattern comprising a first area comprising the compound with the removable organic group and a second area comprising the compound not having the removable organic group, and (d) selectively depositing an amorphous carbon layer on top of the first area.

公开(公告)号：US10685833B2

公开(公告)日：2020-06-16

申请号：US16190921

申请日：2018-11-14

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Mikhail Krishtab ,  Silvia Armini ,  Ivo Stassen ,  Rob Ameloot

IPC: H01L21/02 ,  H01L21/768

Abstract: Example embodiments relate to selective deposition of metal-organic frameworks. One embodiment includes a method of forming a low-k dielectric film selectively on exposed dielectric locations in a substrate. The method includes selectively depositing a metal-containing film, using an area-selective deposition process, on the exposed dielectric locations using one or more deposition cycles. The method also includes providing, at least once, a vapor of at least one organic ligand to the deposited metal-containing film resulting in a gas-phase chemical reaction thereby obtaining a metal-organic framework which is the low-k dielectric film. The low-k dielectric film has gaps on locations where no metal-containing film was deposited.