公开(公告)号：WO0186715A3

公开(公告)日：2002-09-06

申请号：PCT/DE0101651

申请日：2001-05-03

Applicant: INFINEON TECHNOLOGIES AG ,  HOUDEAU DETLEF ,  HUEBNER HOLGER ,  KRIPESH VAIDYANATHAN

Inventor： HOUDEAU DETLEF ,  HUEBNER HOLGER ,  KRIPESH VAIDYANATHAN

IPC: H01L21/00 ,  H01L21/60

CPC classification number: H01L24/83 ,  H01L21/67138 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05573 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/29101 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29563 ,  H01L2224/2957 ,  H01L2224/29666 ,  H01L2224/29681 ,  H01L2224/29684 ,  H01L2224/83011 ,  H01L2224/8319 ,  H01L2224/832 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00

Abstract: According to the invention, the first metal layer (107) is soldered to the second metal layer (102) using a soldering material (104), whereby only a portion of the first metal layer (107) is transformed into one or more intermetallic phases (122) with the soldering material that is used.

Abstract translation: 第一金属层（107）被焊接到使用焊料材料（104）的第二金属层（102），其中，仅所述第一金属层（107）的一部分被转化成一种或多种金属间相（122）所使用的焊接材料。

公开(公告)号：WO2004086497A3

公开(公告)日：2005-04-21

申请号：PCT/DE2004000544

申请日：2004-03-17

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L21/98 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2924/01068 ,  H01L2924/00014

Abstract: The invention relates to a method for producing a plurality of printed conductor layers (3, 13, 7) on the upper face of one or two semiconductor chips (11, 12), which are separated from one another by insulation layers (14), the latter being constructed in such a way that a printed conductor layer that is applied in the form of a bridge (20) makes contact with printed conductors (3) that have been previously applied. In said method, the design of the semiconductor chips does not have to be adapted to wiring that has only been completed during the production of the semiconductor stack.

Abstract translation: 存在多个导体线路层（3,13，7）上的一个或两个产生的半导体芯片（11,12），它们由绝缘层（14），其被构造成使得一个在每种情况下彼此分离的顶部（作为桥20 ）施加布线层接触先前沉积的导体轨迹（3）。 在这种方法中，半导体芯片的设计不需要被适配为你使半导体奇普·斯塔克布线时作出的第一选择。

公开(公告)号：WO2004064139A2

公开(公告)日：2004-07-29

申请号：PCT/DE0303961

申请日：2003-12-02

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L21/56 ,  H01L25/065 ,  H01L21/98

CPC classification number: H01L21/563 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/4847 ,  H01L2224/73203 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: The invention relates to a semiconductor chip stack, wherein an intermediate gap between the semiconductor chips (1,2) is filled at least along the edge of the top side of the top chip (2) by a spacer (7) made of a photostructurable polymer, a photo-resist of a casting compound or an adhesive and thus outwardly sealed. Terminal contact surfaces (5) for bond wires (6) or other external connections are kept free from the material of said spacer on the top side of the bottom chip (1).

Abstract translation: 在半导体奇普·斯塔克是在半导体芯片之间（1，2）现有的空间沿着由隔板顶部芯片（2）的上表面的一个边缘的至少（7）包括可光成像聚合物，抗蚀剂，密封剂或粘接剂被填充，因此 对外封闭。 在此，接合线（6）或从该间隔件的材料的底部的芯片（1）的上侧的其他的外部连接器端子的接触表面（5）保持自由。

公开(公告)号：WO03003459A3

公开(公告)日：2003-05-30

申请号：PCT/DE0201896

申请日：2002-05-23

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01068 ,  H01L2924/01327 ,  H01L2924/00

Abstract: The invention relates to an arrangement of a semiconductor component on a substrate, whereby the substrate (30) comprises contact surfaces (32) on an assembly side (31). The semiconductor component comprises a first chip (10) and at least one second chip (20), whereby the second chip (20) is arranged on the first chip (10). The first and the second chip (10, 20) are thus electrically connected to each other. Furthermore the first chip (10) comprises contact surfaces (12) on the first main side (11) thereof, with which the above faces the assembly side (31) of the substrate (30). The contact surfaces of the first chip (10) are electrically connected to the corresponding contact surfaces (32) of the substrate (30) by means of a jointing agent.

Abstract translation: 本发明提出的半导体器件的一个基片上的装置包括其中在组件一侧（31）的接触面的基片（30）（32）。 该半导体器件包括：第一芯片（10）和至少一个第二芯片（20），其中，所述第一芯片（10）在所述第二芯片（20）被布置。 所述第一和第二芯片（10，20）电连接在一起。 此外，在它的第一主侧的第一芯片（10）（11）的接触面（12），与它面对基片（30）的装载侧（31）。 经由电连接装置与所述衬底（30）的相互关联的接触表面（32）相关联的所述第一芯片（10）的接触面。

公开(公告)号：WO02067291A3

公开(公告)日：2002-11-14

申请号：PCT/DE0200339

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/4985 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/73204 ,  H01L2224/8182 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/73103 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The contact surfaces (3) of the semi-conductor chip (1) and the substrate are arranged opposite each other and connected together in an electrically conductive manner, the distance between the contact surfaces being less than 10 mu m. In preferred embodiments, said distance is normally only 2 mu m, and can be created according to a diffusion soldering technique (SOLID). Other metallic surfaces (2) are provided so that the semi-conductor chip and the substrate can be joined,

Abstract translation: 的接触面（3）的半导体芯片（1）和基片的彼此相对布置并且电连接到导电彼此，其中所述接触表面之间的距离小于10微米。 在优选的实施方案中，该距离是仅典型地为2对应亩（SOLED）可以通过Diffusionslöttechnik的方法来制备。 对于半导体芯片的基板进一步金属表面的连接和（2）可以存在。

公开(公告)号：WO03107421A2

公开(公告)日：2003-12-24

申请号：PCT/DE0301469

申请日：2003-05-07

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L21/60 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L25/0657 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

Abstract: The invention relates to a semi-conductor component comprising a first chip (10) which has a first flat metallisation (11) on a first main surface (17), also comprising a second chip (20) which has a second flat metallisation (21) on a second main surface (27). The main surfaces (17, 27) of the first and the second chips (10, 20) are orientated opposite each other such that a mechanical connection is produced between the first and the second chips (10, 20) as a result of the opposite lying metallations by means of a soldering layer and at least one of the metallisations (11, 21) is structured.

Abstract translation: 本发明提出了具有在第一主表面的第一芯片（10）（17）具有第一金属化表面（11）的半导体器件，并与在第二主表面的第二芯片（20）的第二区域（27） 金属化（21），前，其中所述第一和第二芯片（10，20）彼此面对，它们的主表面（17，27），使得由相对的金属化（11,21）通过钎焊层的手段，机械连接 所述第一和第二芯片之间（10，20）由与所述金属化（11,21）中的至少一个被结构。

公开(公告)号：WO02095817A3

公开(公告)日：2003-06-19

申请号：PCT/DE0201783

申请日：2002-05-17

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L21/60 ,  H01L23/485 ,  H01L25/065 ,  H01L25/18 ,  H01L21/98

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/8183 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

Abstract: According to the invention, a semiconductor component, with at least one semiconductor chip (20) on a base chip (10) serving as substrate has contact surfaces (11, 21) made of metal on the at least one semiconductor chip (20) and the base chip (10). The semiconductor chip (20) and the base chip (10) are thus arranged relative to each other such that the corresponding contact surfaces of the at least one semiconductor chip (20) and the base chip (10) are facing each other and the facing contact surfaces (11, 21) are electrically connected to each other. The separation between a contact surface of the at least one semiconductor chip (20) and the corresponding contact surface of the base chip (10) is less than 10 microm. The base chip (10) comprises components produced by a first technique, whilst the at least one semiconductor chip (20) comprises components produced by means of a second technique.

Abstract translation: 本发明提出了一种具有在作为衬底的基于芯片（10），其中，所述至少一个半导体芯片（20）和基片（10）的接触表面（11，21）由金属制成的区域中的至少一个半导体芯片（20）的半导体器件。 半导体芯片（20）和基片（10）彼此对齐，使得该至少一个半导体芯片（20）和彼此面对并相互面对的接触表面（11，21）导电地连接到彼此的基片（10）的相互关联的接触表面。 所述至少一个半导体芯片（20）和基片（10）的相关联的接触面的各自的接触表面之间的距离达不到10微摩尔。 基底芯片（10）包含了在第一技术制造，而含有至少一个半导体芯片（20），其在第二技术制造的部件的组件。

公开(公告)号：WO0197285A2

公开(公告)日：2001-12-20

申请号：PCT/DE0101989

申请日：2001-05-28

Applicant: INFINEON TECHNOLOGIES AG ,  HACKE HANS JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX GERHARD ,  TILGNER RAINER

Inventor： HACKE HANS-JUERGEN ,  HUEBNER HOLGER ,  KOENIGER AXEL ,  SEITZ MAX-GERHARD ,  TILGNER RAINER

IPC: H01L21/48 ,  H01L21/60 ,  H01L21/603 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: The invention relates to an electronic component consisting of a housing (1) and a first substrate (2) which has at least one integrated circuit. Several contact surfaces (4) are distributed in an arbitrary manner on the surface of the first substrate (2). The surface of a second substrate (3), which forms a housing, is connected mechanically to the surface of the first substrate (2) by means of an insulating connecting layer (5). Said second substrate (3) has contact connection surfaces (6) which are in direct, electrically conductive contact with the contact surfaces (4) of the first substrate (2), in addition to external contact surfaces (9) positioned symmetrically that are connected in a conductive manner to the contact connection surfaces (6) by means of through contacts (8) in the second substrate (3).

Abstract translation: 本发明涉及一种壳体（1）的电子部件，并具有第一衬底（2）被至少一个集成电路，其中，多个接触表面（4）的所述第一衬底的表面上随机（2）被布置成分布和外壳形成第二 衬底（3）通过一绝缘粘结层（5）与所述第一基片（2）的表面的表面机械地连接，其中，所述第二衬底（3）具有接触垫（6）连接到所述第一基板的所述接触表面（4）（2 ）是平坦的，并且导电地连接到和对称布置外接触面（9），其（经由通过触点8）（在第2基板3）与所述接触垫（6）导电连接。

公开(公告)号：WO03030246A3

公开(公告)日：2003-09-18

申请号：PCT/DE0203506

申请日：2002-09-19

Applicant: INFINEON TECHNOLOGIES AG ,  BERGMANN ROBERT ,  HUEBNER HOLGER

Inventor： BERGMANN ROBERT ,  HUEBNER HOLGER

IPC: B23K1/00 ,  B23K1/005 ,  B23K1/008 ,  B23K1/012 ,  B23K3/08 ,  F24C7/00 ,  F26B19/00 ,  H01L21/00 ,  H01L21/58 ,  H01L21/60 ,  H01L21/603 ,  H05K3/34 ,  H05K13/04

CPC classification number: H01L24/80 ,  B23K1/0056 ,  B23K2201/40 ,  H01L24/26 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/00

Abstract: According to the invention, a chip (4), maintained on a chip support (13) by means of a mandrel (1) is heated by a radiation source (12) on the side opposite to the wafer (2) so as to melt an input soldering metal applied on one side opposite to the wafer. A cleaning device (5) comprising a plate (6) provided with a slot (7), a gas channel (8) and a gas evacuation port (14) located proximate to the slot and designed for a forming gas is placed parallel to the wafer. The chip is moved vertically relative to the wafer, compressed on the wafer through the slot and soldered by isothermal solidification.

Abstract translation: 保持的芯片支撑件（13）绕卡盘（1）的芯片中的一个（4）被加热侧远离（2）在这里具有辐射源的晶片的一个（12），从而使熔化的上面向晶片侧地块的一侧施加的 是。 甲清洗装置（5）配有一个板（6）具有一个窗口在窗口（14），用于合成气体（7），气体通道（8）和一出气口布置安装平行于晶片。 芯片垂直移动到晶圆上，通过窗口压到晶圆上并通过等温固化进行焊接。

公开(公告)号：WO0182370A9

公开(公告)日：2002-09-19

申请号：PCT/EP0103546

申请日：2001-03-28

Applicant: INFINEON TECHNOLOGIES AG ,  HUEBNER HOLGER

Inventor： HUEBNER HOLGER

IPC: H01L21/027 ,  H01L21/02 ,  H01L21/98 ,  H01L25/065 ,  H01L27/12 ,  H01L25/04

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2225/06593 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: During the three-dimensional integration of integrated circuits, a thinned semiconductor substrate (1) is arranged on a second semiconductor substrate and mechanically and electrically connected thereto. Continuous contact holes (24) are formed in the second semiconductor substrate (1) proceeding from a rear side (3) of the substrate to a first metal wiring plane (22) on a front side of the substrate (12). In order to adjust the contact holes (24) on the structures arranged on the front side (2), a structure (4) is disposed on the front side (2) of the substrate (1) and is used as an adjusting mark (7) thereon (2). Said structure (4) is covered with a wear layer (15) and laid bare from the rear side (3) of the substrate (1) outwards so that the structure (4) can also be used as an adjusting mark (7) on the rear side. It is thus possible to avoid making an adjustment error between the structures arranged on the front side (2) and the rear side (3).

Abstract translation: 背景技术在集成电路的三维集成，薄型化的半导体衬底（1）被布置在第二半导体基板上并与之机械和电连接。 为了这个目的，在第二，薄化的半导体衬底（1）是通过接触孔（24）从基板背面侧（3），以在基板正面上的第一金属布线层（22）开始（12）形成。 以调节前面的接触孔配置在（24）（2）结构在所述基板的前侧（2），1层结构（4）（1）被布置在所述前表面（2）和对准标记（7 ）都可以使用。 所述结构（4）是长满耐磨层（15）和开始从（1）露出的基板的背面（3），以便从背面（3）的对准标记（7）的结构（4），可以使用 ， 其特征在于所述位于前（2）和背面（3）避免结构之间的调整误差。