公开(公告)号：JP2003198345A

公开(公告)日：2003-07-11

申请号：JP2002311370

申请日：2002-10-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUTTNER FRANZ

IPC: H03K5/08 ,  H03F1/34 ,  H03F3/45 ,  H03F3/72 ,  H03K17/00 ,  H03K17/693 ,  H03M1/00

Abstract: PROBLEM TO BE SOLVED: To provide a multiplexer operating even in a low-supplying voltage. SOLUTION: An integrated analog multiplexer comprises a plurality of multiplexer inputs (ME1, ME2 and ME3), a multiplexer output (MA), and a difference amplifier (OP) with a switching device (1), an amplifier output (VA) and a reverse amplifier input (NE), and a non-reverse amplifier input (PE). The amplifier output (VA) forms a multiplexer output, the difference amplifier is connected as a reverse amplifier by a feedback loop (2) from the amplifier output (VA) to the reverse amplifier input (NE), and the switching device (1) selectively connects either one of the multiplexer inputs (ME1, ME2 and ME3) to the reverse amplifier input (NE). COPYRIGHT: (C)2003,JPO

公开(公告)号：WO0161862A3

公开(公告)日：2001-12-20

申请号：PCT/EP0101712

申请日：2001-02-15

Applicant: INFINEON TECHNOLOGIES AG ,  KUTTNER FRANZ

Inventor： KUTTNER FRANZ

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/68 ,  H03M1/74

CPC classification number: H03M1/1061 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: The invention relates to a digital/analogue converter, comprising (a) a memory device (4), for the buffer storage of a digital value to be converted with n lower value binary data bits di(0 ; and (d) a calibrating circuit (30), for the calibration of both power source groups (12, 22) such that the sum of all the currents from the second power source group (22) is equal to that current value IQ, created by a power source (15a-15g) of the first power source group (12).

Abstract translation: 校准的数字/模拟转换器包括：（a）存储器装置（4）用于锁存n的要被转换的数字值至少显著二进制数据位二（0

公开(公告)号：WO2005006560B1

公开(公告)日：2005-02-17

申请号：PCT/EP2004007428

申请日：2004-07-07

Applicant: INFINEON TECHNOLOGIES AG ,  KUTTNER FRANZ

Inventor： KUTTNER FRANZ

IPC: H03M1/06 ,  H03M1/68

CPC classification number: H03M1/066 ,  H03M1/685 ,  H03M3/502

Abstract: The invention relates to a digital-analog converter comprising: a DEM logic device (10) for generating at least two digital output data (13, 14) from the digital input data (11) according to a predetermined algorithm while determining a starting cell and end cell in the field arrangement (22), between which cells (24) having energy sources (30) to be activated are located; a decoding device (16) for decoding the at least two digital output data (13, 14) of the DEM device (10) into activating signals (17, 17', 18, 18', 19, 19', 20, 20', 21, 21') for activating the cells (24) to be activated, and; a field arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25') according to the activating signals (17, 17', 18, 18', 19, 19', 20, 20', 21, 21'). The invention also relates to a digital-Analog conversion method.

Abstract translation: 本发明提供一种数字 - 模拟转换器与准备就绪：一个DEM逻辑器件，用于根据预定的算法确定初始小区和在阵列布置的最终细胞，于激活能量源，其单元之间从所述数字输入数据产生的至少两个数字输出数据 说谎; 解码器设备，用于将DEM设备的至少两个数字输出数据解码成驱动信号，用于激活要激活的单元; 以及用于响应于驱动信号输出至少一个量化的模拟信号的单元的现场布置。 本发明还提供了一种数模转换的方法。

公开(公告)号：WO0014883A3

公开(公告)日：2000-05-25

申请号：PCT/DE9902757

申请日：1999-09-01

Applicant: INFINEON TECHNOLOGIES AG ,  KUTTNER FRANZ

Inventor： KUTTNER FRANZ

IPC: H04N5/16 ,  H03F3/45 ,  H03M1/06 ,  H03M1/12

CPC classification number: H03M1/1295 ,  H03M1/0682

Abstract: The invention relates to an evaluation device (4) connected to the output of an A/D converter (3) for comparing the direct component of a digitally converted input signal having a threshold value and at least one power source (13, 14, 17, 18) that may be connected to the differential input (1) by the evaluation device (4) in such a way that the differential input (1) can be loaded or unloaded with a current to increase or reduce the direct component in the direction of the threshold value.

Abstract translation: 它被连接到与A / d转换器的输出（3）评估装置（4）用于一个DC分量进行比较数字与阈值和由所述评估装置（4）连接到差分输入（1）可以以这样的方式连接转换输入信号的至少一个 电流源（13,14,17,18）提供差动输入（1）充电或放电，以用电流增大或减小阈值方向上的DC分量。

公开(公告)号：DE102007061031B4

公开(公告)日：2019-03-28

申请号：DE102007061031

申请日：2007-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUTTNER FRANZ ,  KNOBLINGER GERHARD

IPC: H01L27/06 ,  H01L27/12 ,  H01L29/78

Abstract: Vorrichtung, umfassend:ein Substrat mit einem isolierenden vergrabenen Oxidgebiet,ein erstes MuGFET-Bauteil, welches über dem vergrabenen Oxidgebiet ausgebildet ist und an einem ersten Referenzanschluss mit einer ersten Referenzpotenzialquelle einer ersten Stromversorgung gekoppelt ist,ein zweites MuGFET-Bauteil, welches über dem Substrat ausgebildet ist und an einem zweiten Referenzanschluss mit einer zweiten Referenzpotenzialquelle einer von der ersten Stromversorgung verschiedenen zweiten Stromversorgung gekoppelt ist, undein Kopplungsnetzwerk, welches das erste MuGFET-Bauteil mit dem zweiten MuGFET-Bauteil koppelt,wobei der erste Referenzanschluss und der zweite Referenzanschluss voneinander isoliert sind.

公开(公告)号：DE102008061129A1

公开(公告)日：2009-06-18

申请号：DE102008061129

申请日：2008-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOELLINGER WERNER ,  KUTTNER FRANZ

IPC: H03K17/0812 ,  H02M1/08 ,  H02M1/32 ,  H02M3/157

Abstract: This disclosure relates to monitoring and controlling a voltage characteristic of a Drain Extended Metal Oxide Semiconductor (DeMOS) transistor.

公开(公告)号：DE102008057282A1

公开(公告)日：2009-05-20

申请号：DE102008057282

申请日：2008-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUTTNER FRANZ

IPC: H03M1/74 ,  H03M1/06

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

公开(公告)号：DE102008038454A1

公开(公告)日：2009-02-26

申请号：DE102008038454

申请日：2008-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNOBLINGER GERHARD ,  KUTTNER FRANZ

IPC: H01L27/088 ,  H01L21/8234

公开(公告)号：DE10250632A1

公开(公告)日：2004-05-19

申请号：DE10250632

申请日：2002-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOGNER PETER ,  KUTTNER FRANZ

IPC: H03D7/00

Abstract: A process for mixing a digital signal (4) with a second signal (7) comprises converting the digital signal into an analog current signal (5) using a D/A converter (1) which is then input into a mixer (3) and combined with the second signal. An Independent claim is also included for a mixing circuit for the above process.

公开(公告)号：DE59806661D1

公开(公告)日：2003-01-30

申请号：DE59806661

申请日：1998-03-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUTTNER FRANZ

IPC: H03K5/24 ,  H03F3/45

Abstract: The circuit includes a source follower circuit (7) coupled to a differential amplifier stage (6), and a switch (3) which closes a feedback loop from the source follower to the differential amplifier stage. A diode (11) of the same conductivity type as the transistor serving as a switch is provided for the bias point adjustment of the differential amplifier stage. The diode is preferably an NMOS diode, which is connected between the gate of the source follower transistor and the supply voltage (VSS).