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公开(公告)号：JP2002093148A
公开(公告)日：2002-03-29
申请号：JP2001200212
申请日：2001-06-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105
Abstract: PROBLEM TO BE SOLVED: To provide such a method and arrangement for correcting a parasitic current loss in a memory cell field so as to provide a magnetic field of equal strength to each memory cell. SOLUTION: This purpose is achieved according to this invention by the above method in this field by which the currents supplied to each word line and bit line are so controlled that, at the intersectional points of the memory cells, the total of the currents flowing through the word line and bit line belonging to each intersectional point is substantially constant.
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公开(公告)号：JP2001215256A
公开(公告)日：2001-08-10
申请号：JP2000384321
申请日：2000-12-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
Abstract: PROBLEM TO BE SOLVED: To test a multiplicity of automatically adjusted chips in parallel by improving a chip testing device. SOLUTION: This chip testing device uses a printed circuit board(PCB) and is of the type forming electrical connection between the PCB and the chips to test the plurality of chips in parallel by the PCB. The electrical connection is formed by probe needles mounted directly on the PCB, and the PCB is mounted with additional probe needles acting as dummy needles. Thus, the testing device is formed that is characterized in that the chips are adjusted mechanically and automatically.
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公开(公告)号：JP2003007086A
公开(公告)日：2003-01-10
申请号：JP2002098649
申请日：2002-04-01
Applicant: Infineon Technologies Ag , インフィネオン テヒノロギーズ アーゲー
Inventor： ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUPKE JENS , POECHMUELLER PETER , MUELLER JOCHEN , SCHITTENHELM MICHAEL
CPC classification number: G11C29/48
Abstract: PROBLEM TO BE SOLVED: To provide a test circuit for testing a synchronous memory circuit 3 which is operated with a high clock frequency and which is capable of adjusting test latency.
SOLUTION: This test circuit has a frequency multiplying circuit 4 generating a high frequency clock signal for the synchronous memory chip 3 by multiplying a specific multiplication factor to the frequency of a low frequency clock from the external test unit 2, a test data generator 16 which generates test data based on a data control signal from the external test unit 2 and writes the data in the synchronous memory circuit 3, a first signal delay circuit 19 for delaying the test data by an adjustable first delay time, a second signal delay circuit 24 for delaying data from the circuit 3 to a test circuit 1 by an adjustable second delay time and a data comparing circuit 27 which compares the test data generated by the generator 16 with data from the circuit 3 and outputs a signal indicating whether the circuit 3 can operate or not to the unit 2.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供一种用于测试以高时钟频率操作并且能够调整测试等待时间的同步存储器电路3的测试电路。 解决方案：该测试电路具有通过将特定乘法因子与来自外部测试单元2的低频时钟频率相乘的同步存储器芯片3产生高频时钟信号的倍频电路4，测试数据产生器16 基于来自外部测试单元2的数据控制信号生成测试数据，并将数据写入同步存储器电路3，第一信号延迟电路19，用于将测试数据延迟可调节的第一延迟时间;第二信号延迟电路24 用于通过可调节的第二延迟时间将电路3到测试电路1的数据延迟到数据比较电路27，数据比较电路27将由发生器16产生的测试数据与来自电路3的数据进行比较，并输出指示电路3是否可以 操作或不操作本机2。
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公开(公告)号：JP2002093147A
公开(公告)日：2002-03-29
申请号：JP2001202594
申请日：2001-07-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
Abstract: PROBLEM TO BE SOLVED: To make it more reliable to read from a memory cell of an integrated memory provided with a memory cell MC having a magneto resistance memory effect inserted between column lines BL0-BLn and row lines WL0-WLm. SOLUTION: The row lines are connected with a selection line 2, and each row line is connected with a connection terminal GND to a selection signal so as to read a data signal DA of the memory cell connected with the row lines, and the selection circuit is configured so that row lines not connected with the memory cells to read data signals are electrically separated in the selection circuit and is controlled with a control means 4.
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公开(公告)号：JP2001155498A
公开(公告)日：2001-06-08
申请号：JP2000302292
申请日：2000-10-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G11C11/401 , G11C29/00 , G11C29/04 , G11C29/12
Abstract: PROBLEM TO BE SOLVED: To provide a circuit device of a semiconductor memory and a method in which quality of a semiconductor memory being as high as possible can be achieved for a holding time of a memory cell with comparatively slight test, restoration, and repair cost. SOLUTION: Each address of a normal unit to be replaced is stored by memory units corresponded to redundant units respectively, a self-test unit performs a function test of a memory cell by the prescribed holding time of contents of a memory cell, successively, analysis that which of normal units is to be replaced by which of redundant unit is performed.
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Patent Agency Ranking
公开(公告)号：JP2002093189A
公开(公告)日：2002-03-29
申请号：JP2001201076
申请日：2001-07-02
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G11C11/14 , G11C11/15 , G11C29/04 , H01L21/8246 , H01L27/105 , G11C29/00
Abstract: PROBLEM TO BE SOLVED: To properly read and write a data signal from/in remaining memory cells when a defective memory cell causing a short circuit exists across a row line and a column line, in an integrated memory provided with memory cells having a magnetic resistance memory effect. SOLUTION: Column lines BL0-BLn are connected with a read amplifier 3, and to read a data signal DA from a selected memory cell MC3 via the column line BL2 connected with the selected memory cell MC3, or to write the data signal DA in the sel.ected memory cell MC3, row lines WL0-WLm can be connected to a selection signal terminal GND. In that case, one or plural column lines BL0, BL1, BLn which are not connected with the memory cell MC3 are controlled so as to be electrically insulated in a sense amplifier when reading or writing the data signal DA.
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公开(公告)号：JP2001135099A
公开(公告)日：2001-05-18
申请号：JP2000280345
申请日：2000-09-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G01R31/28 , G01R31/3185 , G11C11/22 , G11C11/401 , G11C14/00 , G11C29/12 , G11C29/24 , G11C29/00
Abstract: PROBLEM TO BE SOLVED: To propose an integrated memory in which the function of a reference cell is easily tested. SOLUTION: This memory has memory cells MC in which memories are arranged at an intersections of word lines Wli and bit lines BL, /BL, first reference cells RC1 which are arranged at intersections of at least one reference word line RWL1, RWL1' and the bit lines and which are used for forming reference potentials on the bit lines before data is read out from the memory cell in a normal operation mode, and second reference cells RC2, RC3 which are arranged at intersections of at least one second reference word line RWL2, RWL2', RW3 and the bit lines and are used for forming a reference potential on the bit lines before data is read out form the first reference cell, in a test operation mode.
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公开(公告)号：JP2001135072A
公开(公告)日：2001-05-18
申请号：JP2000278825
申请日：2000-09-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G01R31/28 , G01R31/3185 , G11C11/22 , G11C11/401 , G11C11/4074 , G11C14/00 , G11C29/14 , G11C29/00
Abstract: PROBLEM TO BE SOLVED: To inspect a memory cell by the execution of multiple memory accesses while reducing time. SOLUTION: One electrode in each memory capacitor C in a memory cell MC is connected to one of plural bit lines BLi through a corresponding selection transistor T and the other electrode is connected to one of plate segments PLA, PLB, PLC and PLD. The control terminal of each of the selection transistors T is connected to one of plural word lines WLi. At a normal mode, the potential of only one of plural plate segments is pulsated and the potentials of the two plate segments are simultaneously pulsated at a test mode for accessing the memory cell MC.
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公开(公告)号：JP2000323539A
公开(公告)日：2000-11-24
申请号：JP2000116586
申请日：2000-04-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
Abstract: PROBLEM TO BE SOLVED: To reduce the time required for testing the self-testing circuit of a chip and dispense with an external testing unit by providing a BIST(built-in self testing) unit on a wafer for which a burn-in process is executed. SOLUTION: Many semiconductor chips 2 are arranged on a semiconductor wafer 1, and contact cushions or pads 11 are arranged on these chips 2. Then, pins for a burn-in process to be performed are arranged through these pads 11. As a result, all the burn-in process is controlled by BIST units 7. Each unit 7 is arranged within a cut edge 3 of the corresponding chip 2 to be connected to a bus 4, and to the corresponding cushion or pad 11 for the contact pin using a line 10. As a result, external testing units can be dispensed with, and hence the testing time can be reduced.
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公开(公告)号：JP2000311497A
公开(公告)日：2000-11-07
申请号：JP2000115372
申请日：2000-04-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER
IPC: G11C11/401 , G06F11/20 , G11C11/406 , G11C29/00 , G11C29/44
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a defective memory cell can be replaced by a redundant memory cell without using an expensive external computer. SOLUTION: This semiconductor memory is provided with a BIST(built-in self test) computing unit 14 and a special algorithm for a defective memory cell, word line, and a bit line, and a redundant memory cell, a bit line, and a word line are determined. In this case, a counter unit 15 is provided in the BIST computing unit 14, the counter unit counts up to the upper limit using the number of defective memory cells as a hit value, and when a hit value exceeds the upper limit, a corresponding word line or a bit line is replaced.
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