公开(公告)号：DE102004041679A1

公开(公告)日：2006-02-23

申请号：DE102004041679

申请日：2004-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NUETZEL JOACHIM ,  MUEMMLER KLAUS ,  THIES ANDREAS ,  KAMM FRANK-MICHAEL

IPC: G03F7/00 ,  G03F7/09 ,  H01L21/308 ,  H01L21/8242

Abstract: A method of lithographic production of structures in a radiation-sensitive layer, especially for semiconductor elements, comprises forming a radiation-absorbing layer (1) on or in the substrate (10) and radiating at an angle to the normal so that at least part of the structure in the sensitive layer (20) is shadowed. An independent claim is also included for a structured semiconductor substrate for the above method.

公开(公告)号：DE102005055853A1

公开(公告)日：2006-06-08

申请号：DE102005055853

申请日：2005-11-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THIES ANDREAS ,  MUEMMLER KLAUS

IPC: H01L27/105 ,  G11C7/18 ,  H01L21/8239

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.