公开(公告)号：DE10358356A1

公开(公告)日：2004-07-15

申请号：DE10358356

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： JACUNSKI MARK D ,  TONTI WILLIAM ,  MCSTAY KEVIN ,  MAFFITT THOMAS M ,  HOUGHTON RUSSEL

IPC: G11C8/08

Abstract: An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage ("VT") monitor, a wordline on voltage ("Vpp") generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage ("VWLL") generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

公开(公告)号：WO2009134664A2

公开(公告)日：2009-11-05

申请号：PCT/US2009041477

申请日：2009-04-23

Applicant: IBM ,  LAMOREY MARK C ,  MAFFITT THOMAS M

Inventor： LAMOREY MARK C ,  MAFFITT THOMAS M

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0057

Abstract: A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line (212) associated with a selected phase change element (PCE) (206) to be read; comparing a first voltage on a node (516) of the bit line with a second voltage on a delay node (518), wherein the second voltage represents a delayed voltage with respect to the first voltage due to a resistance/capacitance time constant associated therewith; and determining whether, during the read operation, the first voltage drops below the value of the second voltage; wherein in the event the first voltage drops below the value of the second voltage during the read operation, the PCE (206) is determined to be programmed to an amorphous state and in the event the first voltage does not drop below the value of the second voltage, the PCE (206) is determined to be programmed to a crystalline state.

Abstract translation: 实现PCRAM阵列的自参考读取操作的方法包括将刺激应用于与要被读取的所选择的相变元件（PCE）206相关联的位线（212）; 将位线的节点（516）上的第一电压与延迟节点（518）上的第二电压进行比较，其中第二电压由于与其相关联的电阻/电容时间常数而表示相对于第一电压的延迟电压 ; 以及确定在所述读取操作期间所述第一电压是否低于所述第二电压的值; 其中在所述读取操作期间所述第一电压下降到所述第二电压的值以下的情况下，所述PCE（206）被确定为被编程为非晶状态，并且在所述第一电压不低于所述第二电压的值的情况下 电压，PCE（206）被确定为被编程为结晶状态。