Abstract:
An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage ("VT") monitor, a wordline on voltage ("Vpp") generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage ("VWLL") generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.
Abstract:
A method of implementing a self-referencing read operation for a PCRAM array includes applying a stimulus to a bit line (212) associated with a selected phase change element (PCE) (206) to be read; comparing a first voltage on a node (516) of the bit line with a second voltage on a delay node (518), wherein the second voltage represents a delayed voltage with respect to the first voltage due to a resistance/capacitance time constant associated therewith; and determining whether, during the read operation, the first voltage drops below the value of the second voltage; wherein in the event the first voltage drops below the value of the second voltage during the read operation, the PCE (206) is determined to be programmed to an amorphous state and in the event the first voltage does not drop below the value of the second voltage, the PCE (206) is determined to be programmed to a crystalline state.