公开(公告)号：DE10354717B4

公开(公告)日：2006-09-14

申请号：DE10354717

申请日：2003-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

IPC: H01L21/304 ,  H01L21/768 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/8242

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

公开(公告)号：DE10354717A1

公开(公告)日：2004-07-15

申请号：DE10354717

申请日：2003-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

IPC: H01L21/304 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

公开(公告)号：JPH11288906A

公开(公告)日：1999-10-19

申请号：JP5923599

申请日：1999-03-05

Applicant: SIEMENS AG ,  IBM

Inventor： WISE MICHAEL L ,  STEPHENS JEREMY K ,  HEDGE SURI G

IPC: H01L21/304 ,  B24B37/30 ,  B24B49/14 ,  H01L21/3105 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To reduce or remove the nonuniformity in polishing speed between chemical and mechanical polishing(CMP) methods, by providing a device which raises the with temperature of the first part of a semiconductor wafer with respect to the temperature of a second part of the semiconductor wafer. SOLUTION: A part of a wafer carrier 15 is heated up or cooled down by a temperature controller. Annular heating tapes 18 and 19 are attached to the back side 16 of the carrier 15 to perform local heating. When the heating tapes 18 and 19 are activated, heat is conducted through a wafer carrier 15, and imparts different heatings to the wafer wafer. Accordingly for example, the part 10a of the wafer 10 is cooler than the adjacent part 10b which is affected by the heating tape 19. The part 10b is relatively hot, when it is compared with the adjacent part 10a which is not affected by the heating tapes 18 and 19. The part 10b is maintained at a temperature higher than these of the parts 10c and 10e by receiving the affection of the heating tape 18.