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    Method for manufacturing semiconductor device
    1.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09412657B2

    公开(公告)日：2016-08-09

    申请号：US14943706

    申请日：2015-11-17

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

    IPC: H01L21/4763 ,  H01L21/768

    CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827

    Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

    Abstract translation: 在制造半导体的方法中，透明硅（TSV）模板晶片和生产晶片形成夹层结构，其中TSV模板晶片具有均匀分布在其中的TSV结构，用于在生产晶片之间提供电连接以形成3D互连 。 通过减薄半导体晶片获得TSV模板晶片，这有助于降低蚀刻和填充的难度。 在TSV模板晶片上提供连接部件，以方便上层和下面的生产晶圆之间的互连，这有助于降低对准难度，并提高3D设备电气连接设计的便利性。

    Semiconductor devices with a gate conductor formed as a spacer, and methods for manufacturing the same
    2.
    发明授权
    Semiconductor devices with a gate conductor formed as a spacer, and methods for manufacturing the same 有权
    具有形成为间隔物的栅极导体的半导体器件及其制造方法

    公开(公告)号：US09331182B2

    公开(公告)日：2016-05-03

    申请号：US14151441

    申请日：2014-01-09

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

    IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

    Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one aspect, the method comprises forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask. Then, forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. Then, removing a portion of the second shielding layer which is next to the other of the source and drain regions. Lastly, forming a first gate dielectric layer, a floating gate layer, and a second gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.

    Abstract translation: 公开了半导体装置及其制造方法。 一方面，该方法包括在衬底上形成第一屏蔽层，并且将第一屏蔽层作为掩模形成源区和漏区之一。 然后，在衬底上形成第二屏蔽层，并且用第二屏蔽层作为掩模形成源区和漏区中的另一个。 然后，去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。 最后，形成第一栅极电介质层，浮栅层和第二栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150054074A1

    公开(公告)日：2015-02-26

    申请号：US14389095

    申请日：2012-10-08

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/6653 ,  H01L21/28079 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/823842 ,  H01L27/11568 ,  H01L29/105 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2029/42388

    Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

    Abstract translation: 提供半导体器件及其制造方法。 在一个实施例中，该方法可以包括：在衬底上形成第一屏蔽层; 以所述第一屏蔽层为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 在所述第二屏蔽层的侧壁上形成屏蔽间隔物; 用第二屏蔽层和屏蔽间隔物作为掩模形成源极和漏极区域中的另一个; 去除所述屏蔽间隔物的至少一部分; 以及形成栅极电介质层，并且在所述第二屏蔽层的侧壁或所述屏蔽间隔物的可能的剩余部分上形成作为间隔物的栅极导体。

    Semiconductor arrangement having continuous spacers and method of manufacturing the same
    4.
    发明授权
    Semiconductor arrangement having continuous spacers and method of manufacturing the same 有权

    公开(公告)号：US11251183B2

    公开(公告)日：2022-02-15

    申请号：US17039755

    申请日：2020-09-30

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huilong Zhu ,  Yanbo Zhang ,  Huicai Zhong

    IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

    Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

    Semiconductor structure and method for manufacturing the same
    6.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号：US09379056B2

    公开(公告)日：2016-06-28

    申请号：US14423020

    申请日：2012-09-17

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Huicai Zhong ,  Qingqing Liang

    IPC: H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.

    Abstract translation: 本发明提供一种制造半导体结构的方法，包括：a）在衬底上形成金属互连衬垫; b）形成掩模层以覆盖金属互连衬里并在掩模层上形成露出金属互连衬套的开口; c）经由开口蚀刻和断开金属互连衬套，由此绝缘和隔离金属互连衬套。 本发明还提供一种半导体结构，其包括衬底和金属互连衬套，其中金属互连衬里的端部通过在衬底内形成的绝缘壁而断开。 本发明提供的结构和方法有利于缩短相邻金属互连衬套的端部之间的距离，节省器件面积并抑制金属互连衬套发生的短路。

    Semiconductor arrangement having continuous spacers and method of manufacturing the same
    8.
    发明授权
    Semiconductor arrangement having continuous spacers and method of manufacturing the same 有权

    公开(公告)号：US11251184B2

    公开(公告)日：2022-02-15

    申请号：US17039770

    申请日：2020-09-30

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Huilong Zhu ,  Yanbo Zhang ,  Huicai Zhong

    IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

    Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

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