公开(公告)号：US12096623B2

公开(公告)日：2024-09-17

申请号：US17309775

申请日：2019-04-09

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC: H10B41/27 ,  H01L29/423 ,  H01L29/788

CPC classification number: H10B41/27 ,  H01L29/42324 ,  H01L29/788

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US20220085043A1

公开(公告)日：2022-03-17

申请号：US17309775

申请日：2019-04-09

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC: H01L27/11556 ,  H01L29/423 ,  H01L29/788

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US10141408B2

公开(公告)日：2018-11-27

申请号：US14651980

申请日：2014-03-18

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Kunpeng Jia ,  Yajuan Su ,  Huilong Zhu ,  Chao Zhao

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/167 ,  H01L21/265 ,  H01L21/266 ,  H01L21/283 ,  H01L29/45 ,  H01L21/426 ,  H01L21/441 ,  H01L21/477 ,  H01L21/324 ,  H01L21/285

Abstract: A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.