公开(公告)号：US20220122997A1

公开(公告)日：2022-04-21

申请号：US17310282

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Tiancheng GONG ,  Ming LIU

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L25/065

Abstract: Disclosed is a memory, including a plurality of memory units, wherein each memory unit includes: a bulk substrate; a source electrode, a drain electrode and a channel region extending between a source region and a drain region that are located on the bulk substrate; a deep-level defect dielectric layer on the channel region; and a gate electrode on the deep-level defect dielectric layer. The memory of the present disclosure allows the memory unit to operate in the charge trapping mode and the polarization inversion mode. Therefore, the memory has functions of both DRAM and NAND, and combines the advantages of the two.

公开(公告)号：US20220115052A1

公开(公告)日：2022-04-14

申请号：US17426053

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing LV ,  Qing LUO ,  Xiaoxin XU ,  Tiancheng GONG ,  Ming LIU

IPC: G11C11/22 ,  G11C16/14 ,  G11C16/34

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.