公开(公告)号：US12002500B2

公开(公告)日：2024-06-04

申请号：US17426053

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing Lv ,  Qing Luo ,  Xiaoxin Xu ,  Tiancheng Gong ,  Ming Liu

IPC: G11C11/22 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C16/14 ,  G11C16/3404

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

公开(公告)号：US20220093150A1

公开(公告)日：2022-03-24

申请号：US17424998

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing Lv ,  Qing Luo ,  Xiaoxin Xu ,  Tiancheng Gong ,  Ming Liu

IPC: G11C11/22 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/51 ,  H01L29/78 ,  G06N3/063

Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.

公开(公告)号：US11776607B2

公开(公告)日：2023-10-03

申请号：US17424998

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing Lv ,  Qing Luo ,  Xiaoxin Xu ,  Tiancheng Gong ,  Ming Liu

IPC: G11C11/22 ,  H01L29/78 ,  G06N3/063 ,  H01L29/51 ,  H10B51/20 ,  H10B51/30

CPC classification number: G11C11/223 ,  G06N3/063 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.