公开(公告)号：US20150287808A1

公开(公告)日：2015-10-08

申请号：US14435616

申请日：2012-10-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/30625 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78621

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate (200) comprising, from bottom to top, a base layer (201), a buried insulator layer (202), and a surface active layer (203); forming a gate stack on the substrate; removing the surface active layer (203) on both sides of the gate stack and removing a part of the buried insulator layer (202) to form an opening (240); filling the opening (240) with semiconductor materials so as to form source/drain regions (250). Correspondingly, a semiconductor structure is also disclosed. In the present disclosure, by extending the source/drain region to the buried insulator layer of the substrate, the source/drain series resistance is reduced while not increasing parasitic capacitance between the gate and the source/drain regions.

Abstract translation: 公开了半导体结构的制造方法。 该方法包括：提供从底部到顶部包括基底层（201），掩埋绝缘体层（202）和表面活性层（203）的SOI衬底（200）。 在基板上形成栅叠层; 去除所述栅极堆叠的两侧上的表面有源层（203）并且去除所述掩埋绝缘体层（202）的一部分以形成开口（240）; 用半导体材料填充开口（240）以形成源/漏区（250）。 相应地，还公开了一种半导体结构。 在本公开中，通过将源极/漏极区域延伸到衬底的掩埋绝缘体层，源极/漏极串联电阻降低，同时不增加栅极和源极/漏极区域之间的寄生电容。

公开(公告)号：US09343530B2

公开(公告)日：2016-05-17

申请号：US14435624

申请日：2012-10-25

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/772

CPC classification number: H01L29/0692 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02667 ,  H01L21/30625 ,  H01L21/31055 ,  H01L29/66795

Abstract: The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer (210); forming a second dielectric layer (220), the material of the portion where the second dielectric layer is adjacent to the first dielectric layer being different from that of the first dielectric layer (210); forming an opening (230) through the second dielectric layer (220) and the first dielectric layer (2100, the opening portion exposing the substrate; filling a semiconductor material in the opening (230); and removing the second dielectric layer (220) to form a fin structure. In the present invention, the height of the fin structure in the FinFET is controlled by the thickness of the dielectric layer. The etching stop can be controlled well by using the etching selectivity between different materials, which can achieve etching uniformity better compared to time control.

Abstract translation: 本发明提供一种制造FinFET鳍片结构的方法，包括：提供衬底（200）; 形成第一介电层（210）; 形成第二电介质层（220），所述第二电介质层与所述第一电介质层相邻的部分的材料与所述第一介电层（210）的材料不同; 通过第二介电层（220）和第一介电层（2100，露出基板的开口部分;在开口中填充半导体材料）形成开口（230）;以及将第二介电层（220）移除到 在本发明中，FinFET中的翅片结构的高度由电介质层的厚度来控制，通过使用不同材料之间的蚀刻选择性可以很好地控制蚀刻停止，可以实现蚀刻均匀性 比时间控制更好。

公开(公告)号：US20150270341A1

公开(公告)日：2015-09-24

申请号：US14435624

申请日：2012-10-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC: H01L29/06 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0692 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02667 ,  H01L21/30625 ,  H01L21/31055 ,  H01L29/66795

Abstract: The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer (210); forming a second dielectric layer (220), the material of the portion where the second dielectric layer is adjacent to the first dielectric layer being different from that of the first dielectric layer (210); forming an opening (230) through the second dielectric layer (220) and the first dielectric layer (2100, the opening portion exposing the substrate; filling a semiconductor material in the opening (230); and removing the second dielectric layer (220) to form a fin structure. In the present invention, the height of the fin structure in the FinFET is controlled by the thickness of the dielectric layer. The etching stop can be controlled well by using the etching selectivity between different materials, which can achieve etching uniformity better compared to time control.

Abstract translation: 本发明提供一种制造FinFET鳍片结构的方法，包括：提供衬底（200）; 形成第一介电层（210）; 形成第二电介质层（220），所述第二电介质层与所述第一电介质层相邻的部分的材料与所述第一介电层（210）的材料不同; 通过第二介电层（220）和第一介电层（2100，露出基板的开口部分;在开口中填充半导体材料）形成开口（230）;以及将第二介电层（220）移除到 在本发明中，FinFET中的翅片结构的高度由电介质层的厚度来控制，通过使用不同材料之间的蚀刻选择性可以很好地控制蚀刻停止，可以实现蚀刻均匀性 比时间控制更好。