公开(公告)号：US20240194598A1

公开(公告)日：2024-06-13

申请号：US18532246

申请日：2023-12-07

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng GAO ,  Weibing LIU ,  Junjie LI ,  Na ZHOU ,  Tao YANG ,  Junfeng LI ,  Jun LUO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226

Abstract: A metal interconnection structure of a semiconductor device and a method for forming the same. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive structure in the first dielectric layer; etching back part of the first conductive structure; forming an etch stop layer on the first conductive structure; forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and forming a second conductive structure in the second dielectric layer, where the second conductive structure is electrically connected to the first conductive structure.

公开(公告)号：US20250063713A1

公开(公告)日：2025-02-20

申请号：US18799167

申请日：2024-08-09

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jianfeng GAO ,  Weibing LIU ,  Junjie LI ,  Na ZHOU ,  Tao Yang ,  Junfeng LI ,  Jun LUO

IPC: H10B12/00

Abstract: The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.