公开(公告)号：US20220085043A1

公开(公告)日：2022-03-17

申请号：US17309775

申请日：2019-04-09

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC: H01L27/11556 ,  H01L29/423 ,  H01L29/788

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US12183807B2

公开(公告)日：2024-12-31

申请号：US17783624

申请日：2021-12-23

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Weixing Huang ,  Huilong Zhu

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

公开(公告)号：US12274069B2

公开(公告)日：2025-04-08

申请号：US17783627

申请日：2021-12-23

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Weixing Huang ,  Huilong Zhu

IPC: H10B51/30 ,  H10B51/10 ,  H10B51/20

Abstract: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. The C-shaped ferroelectric layer serves as a memory layer of the memory device.

公开(公告)号：US12096623B2

公开(公告)日：2024-09-17

申请号：US17309775

申请日：2019-04-09

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC: H10B41/27 ,  H01L29/423 ,  H01L29/788

CPC classification number: H10B41/27 ,  H01L29/42324 ,  H01L29/788

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US20230352585A1

公开(公告)日：2023-11-02

申请号：US18042612

申请日：2021-03-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Weixing Huang

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/66545

Abstract: Disclosed are a semiconductor device with a ferroelectric or negative capacitance material layer on a sidewall of a gate electrode, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to embodiments, the semiconductor device may include: a substrate; a gate electrode formed on the substrate; a ferroelectric or negative capacitance material layer formed on a sidewall of the gate electrode; and a source region and a drain region that are located on opposite sides of the gate electrode on the substrate.