公开(公告)号：US09716175B2

公开(公告)日：2017-07-25

申请号：US14437506

申请日：2012-11-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.

公开(公告)号：US09691899B2

公开(公告)日：2017-06-27

申请号：US14439179

申请日：2012-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/027 ,  H01L21/308 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located above the base region (100), and the base region (100) is supported above the substrate (130) by the support structure (131), wherein the support structure (131) has a sigma-shaped lateral cross-section; an isolation structure (123) is formed below edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and a source/drain region is formed on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also provided.

公开(公告)号：US20140217421A1

公开(公告)日：2014-08-07

申请号：US14001216

申请日：2012-11-27

Applicant: Institute of Microelectronics Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78654

Abstract: The present invention provides a semiconductor structure comprising a substrate, a gate stack, a sidewall, a base region, source/drain regions, and a support structure, wherein: the base region is located above the substrate, and is separated from the substrate by the void; said support structure is located on both sides of the void, in which part of the support isolation structure is connected with the substrate; the gate stack is located above the base region, said sidewall surrounding the gate stack; said source/drain regions are located on both sides of the gate stack, the base region and the support isolation structure, in which the stress in the source/drain regions first gradually increases and then gradually decreases along the height direction from the bottom. The present invention also provides a manufacturing method for the semiconductor structure. The present invention is beneficial to suppress the short channel effect, as well as to provide an optimum stress to the channel.

Abstract translation: 本发明提供了一种半导体结构，其包括基板，栅极叠层，侧壁，基极区域，源极/漏极区域和支撑结构，其中：基极区域位于衬底上方，并且通过 虚空; 所述支撑结构位于所述空隙的两侧，所述支撑隔离结构的一部分与所述基板连接; 所述栅极堆叠位于所述基极区域的上方，所述侧壁围绕所述栅极叠层; 所述源极/漏极区域位于栅极叠层，基极区域和支撑隔离结构的两侧，其中源极/漏极区域中的应力首先逐渐增加，然后沿着从底部的高度方向逐渐减小。 本发明还提供了一种半导体结构的制造方法。 本发明有利于抑制短通道效应，以及为通道提供最佳应力。

公开(公告)号：US20140004672A1

公开(公告)日：2014-01-02

申请号：US14023426

申请日：2013-09-10

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7848

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.

Abstract translation: 晶体管及其形成方法技术领域本发明涉及晶体管及其形成方法。 本发明的晶体管包括半导体衬底; 形成在所述半导体衬底上的栅介电层; 形成在栅介质层上的栅极; 栅介电层下的沟道区; 以及位于所述半导体衬底中以及在所述沟道区的相应侧上的源极区和漏极区，其中所述源极和漏极区中的至少一个包括与所述沟道区相邻并且沿垂直方向布置的一组位错 到半导体衬底的顶表面，并且该位错组包括至少两个位错。

公开(公告)号：US20130154097A1

公开(公告)日：2013-06-20

申请号：US13712427

申请日：2012-12-12

Applicant: Institute of Microelectronics Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L23/522

CPC classification number: H01L23/522 ,  H01L21/32051 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 该方法包括：提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。 本发明适用于制造集成电路中的互连。

公开(公告)号：US09401425B2

公开(公告)日：2016-07-26

申请号：US14437755

申请日：2012-11-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

Abstract translation: 公开了半导体结构。 半导体结构包括：衬底（130），支撑结构（131），基极区（100），栅极堆叠，间隔物（240）和源极/漏极区，其中栅极堆叠位于 基部区域（100），并且所述基部区域（100）由所述支撑结构（131）支撑在所述基板（130）上，其中所述支撑结构（131）的侧壁横截面为凹曲线 ; 隔离结构（123）形成在基部区域（100）的两侧的边缘之下，其中隔离结构（123）的一部分连接到基板（130）; 在隔离结构（123）和支撑结构（131）之间形成空腔（112）; 并且至少在基极区域（100）和隔离结构（123）的两侧存在源极/漏极区域。 因此，还公开了一种用于制造半导体结构的方法。

公开(公告)号：US20150255594A1

公开(公告)日：2015-09-10

申请号：US14437506

申请日：2012-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.

Abstract translation: 提供准纳米线晶体管及其制造方法，所述准纳米线晶体管包括：提供包括衬底层（100），BOX层（120）和SOI层（130）的SOI衬底; 在所述SOI层上形成基本的翅片结构，所述基本鳍结构包括至少一个硅/硅 - 锗堆叠; 在基本翅片结构的两侧形成源/漏区（110）; 从基本翅片结构和SOI层形成准纳米线翅片; 并在准纳米线翅片上形成栅极叠层。 该方法可以有效地控制栅极长度特性。 还提供了通过上述方法形成的半导体结构。

公开(公告)号：US09023706B2

公开(公告)日：2015-05-05

申请号：US14023426

申请日：2013-09-10

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7848

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.

Abstract translation: 晶体管及其形成方法技术领域本发明涉及晶体管及其形成方法。 本发明的晶体管包括半导体衬底; 形成在所述半导体衬底上的栅介电层; 形成在栅介质层上的栅极; 栅介电层下的沟道区; 以及位于所述半导体衬底中以及在所述沟道区的相应侧上的源极区和漏极区，其中所述源极和漏极区中的至少一个包括与所述沟道区相邻并且沿垂直方向布置的一组位错 到半导体衬底的顶表面，并且该位错集包括至少两个位错。

公开(公告)号：US20150270399A1

公开(公告)日：2015-09-24

申请号：US14439165

申请日：2013-07-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate, which comprises, from top to bottom, an SOI layer (100), a BOX layer (110) and a base layer (130); forming a dummy gate stack on the SOI substrate and an implantation barrier layer on both sides of the dummy gate stack; removing the dummy gate stack to form a gate recess (220); and performing, via the gate recess (220), implantation of stress inducing ions to the semiconductor structure and annealing to form, right below the gate recess (220), a stress inducing region (150) under the BOX layer (110) of the SOI substrate. Accordingly, the present invention further provides a semiconductor structure manufactured according to the above method.

Abstract translation: 公开了半导体结构的制造方法。 该方法包括：提供SOI衬底，其从顶部到底部包括SOI层（100），BOX层（110）和基底层（130）; 在SOI衬底上形成虚拟栅极堆叠，在虚设栅极叠层的两侧形成注入阻挡层; 去除所述虚拟栅极堆叠以形成栅极凹部（220）; 以及通过所述栅极凹槽（220），将引入离子的应力注入所述半导体结构并在所述栅极凹部（220）的正下方）退火以形成在所述栅极凹部（220）的所述BOX层（110）下方的应力诱导区域（150） SOI衬底。 因此，本发明还提供根据上述方法制造的半导体结构。

公开(公告)号：US20150279992A1

公开(公告)日：2015-10-01

申请号：US14437401

申请日：2012-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin ,  Qingqing Liang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/32115 ,  H01L21/845 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Abstract translation: 本发明提供了一种制造鳍式场效应晶体管的方法，包括：提供包括衬底层（100），BOX层（120）和SOI层（130）的SOI衬底; 从SOI层形成基本的翅片结构; 在基本翅片结构的两侧形成源/漏区（110）; 在基极鳍结构的源/漏区（110）之间形成翅片结构; 并且跨过翅片结构形成栅极堆叠。 本发明提供的鳍状场效应晶体管的制造方法可以将高k栅极电介质层，金属栅极和应力源极/漏极区域集成到鳍状场效应晶体管中，以增强半导体器件的性能。