公开(公告)号：WO2012108919A3

公开(公告)日：2012-09-27

申请号：PCT/US2011061283

申请日：2011-11-17

Applicant: INTEL CORP ,  BENNETT JOSEPH A ,  LI GUOGING ,  SOMAYAZULU VALLABHAJOSYULA S ,  HAYEK GEORGE R ,  PRAT GIDEON ,  KAMBHATLA SRIKANTH

Inventor： BENNETT JOSEPH A ,  SOMAYAZULU VALLABHAJOSYULA S ,  HAYEK GEORGE R ,  PRAT GIDEON ,  KAMBHATLA SRIKANTH

IPC: H04L12/56 ,  H04L29/06 ,  H04N7/24

CPC classification number: H04L69/22 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/643

Abstract: A data packet or payload defined by a first format, is generated and is wrapped with headers as defined by a second format, and is processed through a pass through mechanism for transmission based on the second format. The processing includes adding or encapsulating the payload in the transmission data packet. When receiving the transmitted data packet, the theaders may be parsed, and the payload processed.

Abstract translation: 生成由第一格式定义的数据分组或有效负载，并且用由第二格式定义的报头进行封装，并且通过基于第二格式进行传输的传递机制进行处理。 处理包括在传输数据分组中添加或封装有效载荷。 当接收到传输的数据包时，可以解析这些头部，并且处理净荷。

公开(公告)号：AU8377098A

公开(公告)日：1999-04-12

申请号：AU8377098

申请日：1998-06-26

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/28 ,  G06F3/00

Abstract: A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

公开(公告)号：DE19882696B4

公开(公告)日：2007-05-24

申请号：DE19882696

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/10 ,  G06F12/00 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

公开(公告)号：AU8510698A

公开(公告)日：1999-04-23

申请号：AU8510698

申请日：1998-07-22

Applicant: INTEL CORP

Inventor： BENNETT JOSEPH A ,  ABRAMSON DARREN ,  DERR MICHAEL ,  BOGIN ZOHAR

IPC: G06F13/36 ,  G06F13/14

Abstract: A method and apparatus is disclosed for providing an interlocked broadcast message that solves the problem of a system component taking action in response to a broadcast message issued by a processor before the processor receives communication that the broadcast message has been delivered. A broadcast message transaction request is issued from a processor. The broadcast message transaction request is posted in a transaction request buffer. A reply is communicated to the processor that the broadcast message transaction request has been posted, and the broadcast message is then delivered over the bus. In an alternative embodiment, after the broadcast message transaction request is issued from the processor, the broadcast message transaction request is stored in a transaction request buffer. The broadcast message is only delivered over the bus once it has been determined that the reply to the processor that the broadcast message transaction has completed can be immediately delivered to the processor following the delivery of the broadcast message.

公开(公告)号：GB2345170B

公开(公告)日：2002-12-18

申请号：GB0007301

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/10 ,  G06F13/42 ,  G06F9/445

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

公开(公告)号：GB2345170A

公开(公告)日：2000-06-28

申请号：GB0007301

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/10 ,  G06F13/42 ,  G06F9/445

Abstract: A system having a bus (124) coupled to a host (102) and a memory device (108). The bus (124) may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device (108) may store system start-up information and communicate this information with the host (102) over the bus (124).

公开(公告)号：EP1021756A4

公开(公告)日：2000-12-20

申请号：EP98934188

申请日：1998-06-26

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/28 ,  G06F3/00

CPC classification number: G06F13/28

Abstract: A system including a host (102) coupled to a memory device (108) and a peripheral controller device (120). The host (102) is coupled to the peripheral controller device (120) via bus (124) having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device (120) performs a direct memory access (DMA) transactions with the memory device (108) via the host (102) the bus (124).

Abstract translation: 一种包括耦合到存储器设备（108）和外围控制器设备（120）的主机（102）的系统。 主机（102）经由具有多个通用信号线的总线（124）耦合到外围控制器设备（120），以携带时分多路复用的地址，数据和控制信息。 外围控制器设备（120）经由主机（102）与总线（124）执行与存储器设备（108）的直接存储器访问（DMA）事务。

公开(公告)号：EP2673924A4

公开(公告)日：2014-12-10

申请号：EP11858334

申请日：2011-11-17

Applicant: INTEL CORP ,  LI GUOGING

Inventor： BENNETT JOSEPH A ,  SOMAYAZULU VALLABHAJOSYULA S ,  HAYEK GEORGE R ,  PRAT GIDEON ,  KAMBHATLA SRIKANTH

IPC: H04L29/06 ,  H04N7/24 ,  H04L12/56

CPC classification number: H04L69/22 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/643

公开(公告)号：HK1028459A1

公开(公告)日：2001-02-16

申请号：HK00107601

申请日：2000-11-27

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/28 ,  G06F

Abstract: A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

公开(公告)号：HK1026489A1

公开(公告)日：2000-12-15

申请号：HK00105694

申请日：2000-09-09

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/16 ,  G06F13/42 ,  G06F

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.