公开(公告)号：WO2004038583A2

公开(公告)日：2004-05-06

申请号：PCT/US0328783

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/00 ,  G06F9/45 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F12/0897

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a perdetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

Abstract translation: 公开了用于管理第一高速缓存的旁路的方法和设备。 在一个这样的方法中，识别具有大于或等于预定阈值的预期延迟的加载指令。 然后请求安排所识别的加载指令具有预定的等待时间。 然后计划软件程序。 然后将与预定软件程序中的加载指令相关联的实际等待时间与预定等待时间进行比较。 如果实际等待时间大于或等于预定等待时间，则加载指令被标记为绕过第一高速缓存。

公开(公告)号：WO2004038583A9

公开(公告)日：2005-06-09

申请号：PCT/US0328783

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/00 ,  G06F9/45 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F12/0897

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a perdetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

Abstract translation: 公开了管理第一高速缓存的旁路的方法和装置。 在一种这样的方法中，识别具有大于或等于预定阈值的预期等待时间的加载指令。 然后进行请求以将所识别的加载指令调度为具有不确定的等待时间。 然后安排软件程序。 然后将与预定软件程序中的加载指令相关联的实际延迟与预定延迟进行比较。 如果实际延迟大于或等于预定延迟，则加载指令被标记为绕过第一高速缓存。

公开(公告)号：WO03029972A8

公开(公告)日：2004-11-04

申请号：PCT/US0227985

申请日：2002-08-30

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/38

CPC classification number: G06F8/445 ,  G06F8/443

Abstract: A method and apparatus for providing compiler transformation of code using regions with simplified data and control flow and value specialization are described. In one embodiment, the method includes identifying in the code a plurality of potential candidates for value specialization, selecting a group of candidates from the plurality of potential candidates based on a value profile associated with each potential candidate, and determining specialized data for each selected candidate using a corresponding value profile. The method further includes forming a plurality of optimized regions based on corresponding specialized data. Each optimized region includes one or more selected candidates.

公开(公告)号：GB2398141A

公开(公告)日：2004-08-11

申请号：GB0407203

申请日：2002-08-30

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/38

Abstract: A method and apparatus for providing compiler transformation of code using regions with simplified data and control flow and value specialization are described. In one embodiment, the method includes identifying in the code a plurality of potential candidates for value specialization, selecting a group of candidates from the plurality of potential candidates based on a value profile associated with each potential candidate, and determining specialized data for each selected candidate using a corresponding value profile. The method further includes forming a plurality of optimized regions based on corresponding specialized data. Each optimized region includes one or more selected candidates.

公开(公告)号：DE10393481B4

公开(公告)日：2009-02-12

申请号：DE10393481

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/00 ,  G06F12/08

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

公开(公告)号：AU2002332811A1

公开(公告)日：2003-04-14

申请号：AU2002332811

申请日：2002-08-30

Applicant: INTEL CORP A DELAWERE CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/45 ,  G06F9/38

公开(公告)号：GB2410582A

公开(公告)日：2005-08-03

申请号：GB0508442

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/00 ,  G06F9/45 ,  G06F12/08

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a perdetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

公开(公告)号：AU2003288904A1

公开(公告)日：2004-05-13

申请号：AU2003288904

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/00 ,  G06F9/45 ,  G06F12/08

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

公开(公告)号：GB2410582B

公开(公告)日：2006-01-04

申请号：GB0508442

申请日：2003-09-12

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F12/08 ,  G06F9/00 ,  G06F9/45

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

公开(公告)号：HK1074686A1

公开(公告)日：2005-11-18

申请号：HK05106929

申请日：2005-08-11

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  CHEN LI-LING

IPC: G06F9/00 ,  G06F9/45 ,  G06F12/08 ,  G06F

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.