公开(公告)号：WO9956245A3

公开(公告)日：1999-12-16

申请号：PCT/US9909472

申请日：1999-04-29

Applicant: INTEL CORP ,  HSIEH HSIEN CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

Inventor： HSIEH HSIEN-CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

IPC: H03M7/24 ,  G06F13/00

CPC classification number: H03M7/24

Abstract: A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of 128-bit registers (906) in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers (904) in packed format. Color components are assembled for image pixels from the numbers in the integer format.

Abstract translation: 描述用于并行处理图形数据的方法和装置。 许多颜色分量以压缩格式以128位寄存器（906）的至少一个寄存器中以浮点格式存储。 浮点格式的颜色分量将以整数格式转换为数字。 整数格式的数字被放置在一组64位寄存器（904）的至少一个寄存器中。 从整数格式的数字组装图像像素的颜色分量。

公开(公告)号：EP1099168A4

公开(公告)日：2003-04-16

申请号：EP99909866

申请日：1999-03-04

Applicant: INTEL CORP

Inventor： HUFF THOMAS R ,  THAKKAR SHREEKANT ,  HOFFMAN NATHANIEL

IPC: G06F9/30 ,  G06F9/315 ,  G06F9/312 ,  G06F15/80

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30163

Abstract: A method comprises a single instruction (1104) having a first operand identifying a plurality of bytes of packed data (701, 720, 730, 740) and second operand identifiying a corresponding plurality of byte masks. Each of the plurality of byte masks identified by the second operand of the single decoded instruction are analyzed, wherein select bytes of the plurality of bytes identified by the first operand are moved to an implicitly defined location based, at least in part, on the analysis of the individual byte masks identified by the second operand of the single decoded instruction.

公开(公告)号：DE19983189B4

公开(公告)日：2009-12-24

申请号：DE19983189

申请日：1999-04-29

Applicant: INTEL CORP

Inventor： HSIEH HSIEN-CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

IPC: G06T1/20 ,  G06F7/48 ,  H03M7/24

Abstract: Several color components in floating point format are stored in 128-bit register set (906) in packed format. The floating point format of the color components is converted into integer format and is stored in 64-bit register set (904) in packed format. The color components for the pixels are assembled using integer number stored in 64-bit register set. An independent claim is also included for graphics data parallel conversion system.

公开(公告)号：GB2357873B

公开(公告)日：2002-01-09

申请号：GB0105382

申请日：1999-07-15

Applicant: INTEL CORP

Inventor： HACKING LANCE ,  THAKKAR SHREEKANT S ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  HSIEH HSIEN-CHENG E

IPC: G06F12/08 ,  G06F12/0891

公开(公告)号：GB2353881A

公开(公告)日：2001-03-07

申请号：GB0026499

申请日：1999-03-11

Applicant: INTEL CORP

Inventor： ABDALLAH MOHAMMAD A F ,  HSIEH HSIEN-CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

IPC: G06F20060101 ,  G06F7/00 ,  G06F7/38 ,  G06F7/48 ,  G06F9/00 ,  H03M20060101 ,  H03M7/24

Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers (410) in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers (412) in a packed format.

公开(公告)号：GB2343765B

公开(公告)日：2001-02-14

申请号：GB9910126

申请日：1999-04-30

Applicant: INTEL CORP

Inventor： ABDALLAH MOHAMMAD A F ,  HSIEH HSIEN-CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

IPC: G06T1/20 ,  H03M7/24 ,  G06F9/30

Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

公开(公告)号：GB2353881B

公开(公告)日：2003-04-09

申请号：GB0026499

申请日：1999-03-11

Applicant: INTEL CORP

Inventor： ABDALLAH MOHAMMAD A F ,  HSIEH HSIEN-CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

IPC: G06F20060101 ,  G06F7/00 ,  G06F7/38 ,  G06F7/48 ,  G06F9/00 ,  H03M20060101 ,  H03M7/24

公开(公告)号：DE19920214C2

公开(公告)日：2002-04-04

申请号：DE19920214

申请日：1999-04-29

Applicant: INTEL CORP

Inventor： ABDALLAH MOHAMMED A F ,  HUFF THOMAS R ,  ROUSSEL PATRICE ,  HSIEH HSIEN-CHENG E ,  PENTKOWSKI VLADIMIR ,  THAKKAR SHREEKANT S

IPC: G06T1/20 ,  H03M7/24 ,  G06F7/48

Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

公开(公告)号：GB2343029B

公开(公告)日：2002-01-09

申请号：GB9916637

申请日：1999-07-15

Applicant: INTEL CORP

Inventor： HACKING LANCE ,  THAKKAR SHREEKANT S ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  HSIEH HSIEN-CHENG E

IPC: G06F12/08

Abstract: A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.

公开(公告)号：HK1031939A1

公开(公告)日：2001-06-29

申请号：HK01102413

申请日：2001-04-04

Applicant: INTEL CORP

Inventor： HSIEH HSIEN-CHENG E ,  HUFF THOMAS R ,  PENTKOVSKI VLADIMIR ,  ROUSSEL PATRICE ,  THAKKAR SHREEKANT S

IPC: H03M7/24 ,  G06T

Abstract: Several color components in floating point format are stored in 128-bit register set (906) in packed format. The floating point format of the color components is converted into integer format and is stored in 64-bit register set (904) in packed format. The color components for the pixels are assembled using integer number stored in 64-bit register set. An independent claim is also included for graphics data parallel conversion system.