公开(公告)号：JP2011044161A

公开(公告)日：2011-03-03

申请号：JP2010217663

申请日：2010-09-28

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN H ,  VAID KUSHAGRA

IPC: G06F9/52

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

Abstract: PROBLEM TO BE SOLVED: To prevent false contention and serialized execution which may be posed because a capability for executing a plurality of software threads is constantly increasing.
SOLUTION: The apparatus and method are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transactional buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了防止由于执行多个软件线程的能力不断增加而可能引起的错误争用和序列化执行。 解决方案：该设备和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效的远程访问/请求被加载到并被写入共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011028774A

公开(公告)日：2011-02-10

申请号：JP2010217662

申请日：2010-09-28

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN H ,  VAID KUSHAGRA

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

Abstract: PROBLEM TO BE SOLVED: To handle shared memory accesses between a plurality of processors, using lock-free synchronization through transactional execution. SOLUTION: A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to share memory are tracked by a transactional buffer (605). If an invalidating access is encountered, the transaction is re-executed (610). After a pre-determined number of times re-executing the transaction (615), the transaction may be re-executed non-speculatively with locks/semaphores (620). COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：处理多个处理器之间的共享存储器访问，通过事务执行使用无锁定同步。

解决方案：在软件中划分的事务被推测执行。 在执行期间无效远程访问/请求到由共享存储器加载并被写入共享存储器的地址由事务缓冲器（605）跟踪。 如果遇到无效访问，则重新执行事务（610）。 在重新执行事务（615）的预定次数之后，可以非推测地用锁/信号量重新执行事务（620）。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2012024090A3

公开(公告)日：2012-06-07

申请号：PCT/US2011046499

申请日：2011-08-03

Applicant: INTEL CORP ,  KOTTAPALLI SAILESH ,  NEEFS HENK G ,  PAL RAHUL ,  ARORA MANOJ K ,  NAGARAJ DHEEMANTH

Inventor： KOTTAPALLI SAILESH ,  NEEFS HENK G ,  PAL RAHUL ,  ARORA MANOJ K ,  NAGARAJ DHEEMANTH

IPC: G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F12/0833 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/4265 ,  G06F2212/621 ,  G06F2212/622

Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器 关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。 描述和要求保护其他实施例。

公开(公告)号：DE112005002268T5

公开(公告)日：2007-08-23

申请号：DE112005002268

申请日：2005-09-13

Applicant: INTEL CORP

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN

IPC: G06F12/08

公开(公告)号：GB2451200A

公开(公告)日：2009-01-21

申请号：GB0818238

申请日：2005-12-23

Applicant: INTEL CORP

Inventor： CRAWFORD JOHN H ,  VAID KUSHAGRA ,  KOTTAPALLI SAILESH

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/46

Abstract: Disclosed is a multiprocessor core or multi threaded processor, consisting of logic for executing transactions, a shared memory to hold an input data element used by the transaction, a storage element coupled to the logic and the shared memory, a transaction buffer and logic to abort the transaction. The storage element is biased against receiving new data elements during the pendancy of the transaction. The transaction buffer tracks invaliding requests to the shared memory during the execution of the transaction. The transaction abort logic aborts the transaction in response to the transaction buffer tracking an invaliding request during the execution of the transaction. The apparatus may have a second storage element to hold a locking predicate value. When set to a locked value the execution logic is to execute the transaction non-speculatively using a semaphore to provide exclusive access to the data element in the shred memory. The execution logic may evaluate the count variable in response to aborting the transaction and set the locking predicate to the locking value, if the count variable represents that the transaction has been re-executed a predetermined number of times.

公开(公告)号：GB2430288B

公开(公告)日：2007-11-07

申请号：GB0700981

申请日：2005-09-13

Applicant: INTEL CORP

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN

IPC: G06F12/12 ,  G06F12/08

公开(公告)号：GB2437211B

公开(公告)日：2008-11-19

申请号：GB0714433

申请日：2005-12-23

Applicant: INTEL CORP

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN H ,  VAID KUSHAGRA

IPC: G06F9/52 ,  G06F9/46

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

公开(公告)号：DE112005003339T5

公开(公告)日：2007-11-22

申请号：DE112005003339

申请日：2005-12-23

Applicant: INTEL CORP

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN H ,  VAID KUSHAGRA

IPC: G06F9/52 ,  G06F9/46

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

公开(公告)号：GB2430288A

公开(公告)日：2007-03-21

申请号：GB0700981

申请日：2005-09-13

Applicant: INTEL CORP

Inventor： KOTTAPALLI SAILESH ,  CRAWFORD JOHN

IPC: G06F12/12 ,  G06F12/08

Abstract: A method and apparatus for selecting and updating a replacement candidate in a cache is disclosed. In one embodiment, a cache miss may initiate the eviction of a present replacement candidate in a last-level cache. The cache miss may also initiate the selection of a future replacement candidate. Upon the selection of the future replacement candidate, the corresponding cache line may be invalidated in lower-level caches but remain resident in the last-level cache. The future replacement candidate may be updated by subsequent hits to the replacement candidate in the last-level cache prior to a subsequent cache miss.

公开(公告)号：GB2451200B

公开(公告)日：2009-05-20

申请号：GB0818238

申请日：2005-12-23

Applicant: INTEL CORP

Inventor： CRAWFORD JOHN H ,  VAID KUSHAGRA ,  KOTTAPALLI SAILESH

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.