公开(公告)号：WO2012087330A3

公开(公告)日：2013-06-13

申请号：PCT/US2010061995

申请日：2010-12-23

Applicant: INTEL CORP ,  TROBOUGH MARK ,  TIRUVALLUR KRESHAVAN ,  PRUDVI CHINNA ,  LOVIN CHRISTIAN ,  GRAWROCK DAVID ,  NEJEDLO JAY ,  KABADI ASHOK ,  GOFF TRAVIS ,  HALPRIN EVAN J ,  UDAWATTA KAPILA ,  FOO JIUN LONG ,  CHEAH WEE HOO ,  YONG VUI ,  GOPAL SELVAKUMAR RAJA ,  LEE YEN TAT ,  SAMAAN SAMIE B ,  KILLPACK KIP ,  DOBLER NIEL ,  HAKIM NAGIB Z ,  WHITE MICHAEL T ,  MEYER BRIAN ,  PENNER BILL ,  BAUDREXL JOHN ,  WUNDERLICH RUSS ,  KOZACZUK ANTHONY ,  GREALISH JAMES ,  MARKLEY KYLE ,  STOREY TIM ,  MCCONNELL LOREN ,  COOL LYLE ,  KATARIA MUKESH ,  MOHAMMED RAHIMA ,  ZHENG TIEYU ,  XIA AMY ,  SAHA RIDVAN

Inventor： TROBOUGH MARK ,  TIRUVALLUR KRESHAVAN ,  PRUDVI CHINNA ,  LOVIN CHRISTIAN ,  GRAWROCK DAVID ,  NEJEDLO JAY ,  KABADI ASHOK ,  GOFF TRAVIS ,  HALPRIN EVAN J ,  UDAWATTA KAPILA ,  FOO JIUN LONG ,  CHEAH WEE HOO ,  YONG VUI ,  GOPAL SELVAKUMAR RAJA ,  LEE YEN TAT ,  SAMAAN SAMIE B ,  KILLPACK KIP ,  DOBLER NIEL ,  HAKIM NAGIB Z ,  WHITE MICHAEL T ,  MEYER BRIAN ,  PENNER BILL ,  BAUDREXL JOHN ,  WUNDERLICH RUSS ,  KOZACZUK ANTHONY ,  GREALISH JAMES ,  MARKLEY KYLE ,  STOREY TIM ,  MCCONNELL LOREN ,  COOL LYLE ,  KATARIA MUKESH ,  MOHAMMED RAHIMA ,  ZHENG TIEYU ,  XIA AMY ,  SAHA RIDVAN

IPC: G06F11/22 ,  G06F11/36

CPC classification number: G06F11/2733 ,  G06F11/267

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Abstract translation: 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基准级别，硬件钩（Design for Test或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问对被测试的部件/平台进行远程测试和调试。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

公开(公告)号：DE112010006087T5

公开(公告)日：2014-06-26

申请号：DE112010006087

申请日：2010-12-23

Applicant: INTEL CORP

Inventor： TIRUVALLUR KRESHAVAN ,  LOVIN CHRISTIAN ,  GRAWROCK DAVID ,  HALPRIN EVAN J ,  FOO JIUN LONG ,  CHEAH WEE HOO ,  YONG VUI ,  LEE YEN TAT ,  KILLPACK KIP ,  DOBLER NIEL ,  HAKIM NAGIB Z ,  WHITE MICHAEL T ,  MEYER BRIAN ,  WUNDERLICH RUSS ,  KOZACZUK ANTHONY ,  MARKLEY KYLE ,  MCCONNELL LOREN ,  COOL LYLE ,  MOHAMMED RAHIMA ,  ZHENG TIEYU ,  PRUDVI CHINNA ,  GOPAL SELVAKUMAR RAJA ,  PENNER BILL ,  STOREY TIM ,  KATARIA MUKESH ,  SAHA RIDVAN ,  GOFF TRAVIS ,  BAUDREXL JOHN ,  GREALISH JAMES ,  XIA AMY ,  SAMAAN SAMIE B ,  UDAWATTA KAPILA ,  KABADI ASHOK ,  NEJEDLO JAY ,  TROBOUGH MARK

IPC: G06F11/22 ,  G06F11/36

Abstract: Eine Vorrichtung und ein Verfahren zum Bereitstellen einer Architektur zum Testen, zur Validierung und zur Fehlerbereinigung werden hierin beschrieben. Auf einer Ziel- oder Basisebene werden Hardwarehaken (Design-For-Test oder DFx) in Siliziumbauteilen angeordnet und in diese integriert. Ein Controller kann einen abstrahierten Zugriff auf solche Haken beispielsweise über eine Abstraktionsschicht, welche Details der Hardware-DFx auf niedriger Ebene abstrahiert, bereitstellen. Zusätzlich stellt die Abstraktionsschicht durch eine Schnittstelle, wie beispielsweise APIs, Dienste, Routinen und Datenstrukturen für Software-/Präsentationsschichten auf höheren Ebenen bereit, welche dazu in der Lage sind, Testdaten für eine Validierung und eine Fehlerbereinigung einer Einheit/Plattform im Test zu sammeln. Ferner stellt die Architektur der Testarchitektur potentiell einen abgestuften sicheren (mehrere Ebenen von sicherem) Zugriff bereit. Zusätzlich kann ein physikalischer Zugriff auf die Testarchitektur für eine Plattform durch das Verwenden eines vereinheitlichten, bi-direktionalen Testzugriffanschlusses vereinfacht werden, wobei auch potentiell ein Fernzugriff erlaubt wird, um ein Testen und eine Fehlerbereinigung eines Bauteils/einer Plattform im Test aus der Ferne zu ermöglichen. Im Wesentlichen wird hierin ein vollständiger Testarchitekturstapel zum Testen, zur Validierung und zur Fehlerbereinigung elektronischer Bauteile, Einrichtungen und Plattformen beschrieben.

公开(公告)号：GB2493793A

公开(公告)日：2013-02-20

申请号：GB201122290

申请日：2010-12-23

Applicant: INTEL CORP

Inventor： TROBOUGH MARK B ,  TIRUVALLUR KRESHAVAN ,  PRUDVI CHINNA ,  LOVIN CHRISTIAN ,  GRAWROCK DAVID ,  NEJEDLO JAY ,  KABADI ASHOK ,  GOFF TRAVIS ,  HALPRIN EVAN J ,  UDAWATTA KAPILA ,  FOO JIUN LONG ,  CHEAH WEE HOO ,  YONG VUI ,  GOPAL SELVAKUMAR RAJA ,  LEE YEN TAT ,  SAMAAN SAMIE B ,  KILLPACK KIP ,  DOBLER NIEL ,  HAKIM NAGIB Z ,  WHITE MICHAEL T ,  MEYER BRIAN ,  PENNER BILL ,  BAUDREXL JOHN ,  WUNDERLICH RUSS ,  KOZACZUK ANTHONY ,  GREALISH JAMES ,  MARKLEY KYLE ,  STOREY TIM ,  MCCONNELL LOREN ,  COOL LYLE ,  KATARIA MUKESH ,  MOHAMMED RAHIMA ,  ZHENG TIEYU ,  XIA AMY ,  SAHA RIDVAN

IPC: G06F11/36

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

公开(公告)号：EP3100167A4

公开(公告)日：2017-10-25

申请号：EP14880478

申请日：2014-01-29

Applicant: INTEL CORP

Inventor： KOZACZUK ANTHONY ,  TRETHEWEY JAMES ,  KAINE GREG ,  VEERAMONEY MURALI ,  STAFFORD KAREN

IPC: G06F13/14 ,  G06F3/14 ,  G06F13/38 ,  G09G5/00

CPC classification number: G06F3/1423 ,  G06F1/1654 ,  G06F3/0412 ,  G06F3/0482 ,  G06F3/14 ,  G06F3/1446 ,  G09G3/344 ,  G09G5/003 ,  G09G5/14 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2340/0407 ,  G09G2354/00 ,  G09G2356/00 ,  G09G2358/00

Abstract: A computing device is described. The computing device a processor, a bus coupled to the processor, a graphics display device, coupled to the bus, to display graphics data, an interactive display device, coupled to the bus, to display bitmap image data and a manager module to manage the bitmap image data and transmit the bitmap image data to the interactive display device.

公开(公告)号：EP2798435A4

公开(公告)日：2015-09-09

申请号：EP11878507

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： KOZACZUK ANTHONY

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/32 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/172 ,  Y02D10/24

Abstract: Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by an voltage offset value programmed by an offset code received at the control input of the voltage offset block and a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage output register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage level of a selected voltage offset block, at the control output port coupled to the selected voltage offset block.