公开(公告)号：WO2004075034A3

公开(公告)日：2005-09-09

申请号：PCT/US2004000726

申请日：2004-01-12

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  BELMONT BRIAN ,  KUMAR MUTHA ,  JACKSON RILEY ,  DANNEELS GUNNER ,  FORAND RICHARD ,  GUPTA VIVEK ,  HUCKINS JEFFREY ,  FLEMING KRISTOFFER ,  GADAMSETTY UMA

IPC: G06F20060101 ,  G06F1/32 ,  G06F9/06 ,  G06F9/44 ,  G06F13/10

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3293 ,  G06F13/102 ,  G06F13/4072 ,  G10L19/04 ,  H04R1/1091 ,  H04R2201/109 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D50/20

Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.

Abstract translation: 描述了一种计算系统，其包括在所述计算系统在基于非主CPU / OS的非主操作状态下操作时停用的I / O单元接口。 计算系统还包括在计算系统处于基于非主CPU / OS的非操作状态之内的情况下操作功能任务的控制器。 计算系统还包括耦合到I / O单元接口和控制器的I / O单元。

公开(公告)号：GB2413666B

公开(公告)日：2006-10-11

申请号：GB0513567

申请日：2004-01-12

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  BELMONT BRIAN ,  KUMAR MUTHA ,  JACKSON RILEY ,  DANNEELS GUNNER D ,  FORAND RICHARD ,  GUPTA VIVEK ,  HUCKINS JEFFREY ,  FLEMING KRISTOFFER ,  GADAMSETTY UMA

IPC: G06F1/32 ,  G06F20060101 ,  G06F9/06 ,  G06F9/44 ,  G06F13/10

Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.

公开(公告)号：GB2413666A

公开(公告)日：2005-11-02

申请号：GB0513567

申请日：2004-01-12

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  BELMONT BRIAN ,  KUMAR MUTHA ,  JACKSON RILEY ,  DANNEELS GUNNER D ,  FORAND RICHARD ,  GUPTA VIVEK ,  HUCKINS JEFFREY ,  FLEMING KRISTOFFER ,  GADAMSETTY UMA

IPC: G06F20060101 ,  G06F1/32 ,  G06F9/06 ,  G06F9/44 ,  G06F13/10

Abstract: A computing system is described that includes an I/O unit interface that is deactivated while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit that is coupled to both the I/O unit interface and the controller.

公开(公告)号：DE112004000166B4

公开(公告)日：2014-07-03

申请号：DE112004000166

申请日：2004-01-12

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  BELMONT BRIAN ,  KUMAR MUTHA ,  JACKSON RILEY ,  DANNEELS GUNNER ,  FORAND RICHARD ,  GUPTA VIVEK ,  HUCKINS JEFFREY ,  FLEMING KRISTOFFER ,  GADAMSETTY UMA

IPC: G06F13/10 ,  G06F20060101 ,  G06F1/32 ,  G06F9/06 ,  G06F9/44

Abstract: Rechnersystem, das folgendes umfaßt: a) eine Haupt-CPU (401, 901), die innerhalb eines Haupt-CPU/OS-basierten Betriebszustandes (301, 304, 501, 504) angeschaltet ist und basierend auf einem Haupt-Betriebssystem (OS) Software ausführen kann und innerhalb eines Nicht-Haupt-CPU/OS-basierten Betriebszustands (305, 505) abgeschaltet ist, so dass sie nicht basierend auf dem Haupt-OS Software ausführen kann; b) eine Speicher E/A-Steuereinheit (403, 903), die mit der Haupt-CPU gekoppelt ist, wobei die Speicher E/A-Steuereinheit aktiv ist, wenn sich das Rechnersystem in dem Haupt-CPU/OS-basierten Betriebszustand befindet, und deaktiviert ist, während das Rechnersystem innerhalb des Nicht-Haupt-CPU/OS-basierten Betriebszustand arbeitet; c) einen Systemspeicher (404, 904), der mit der Speicher-E/A-Steuereinheit gekoppelt ist, wobei der Systemspeicher aktiv ist, wenn sich das Rechnersystem in dem Haupt-CPU/OS-basierten Betriebszustand befindet, und deaktiviert ist, während das Rechnersystem innerhalb des Nicht-Haupt-CPU/OS-basierten Betriebszustands arbeitet; d) einen Controller (917), der innerhalb des Nicht-Haupt-CPU/OS-basierten Betriebszustands (305) Funktionsaufgaben durchführt, wobei das Rechnersystem weniger Energie während des Nicht-Haupt-CPU/OS-basierten Zustands als während des Haupt-CPU/OS-Zustands verbraucht; ...

公开(公告)号：DE112004000166T5

公开(公告)日：2005-12-01

申请号：DE112004000166

申请日：2004-01-12

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  BELMONT BRIAN ,  KUMAR MUTHA ,  JACKSON RILEY ,  DANNEELS GUNNER ,  FORAND RICHARD ,  GUPTA VIVEK ,  HUCKINS JEFFREY ,  FLEMING KRISTOFFER ,  GADAMSETTY UMA

IPC: G06F20060101 ,  G06F1/32 ,  G06F9/06 ,  G06F9/44 ,  G06F13/10

Abstract: An apparatus is provided that includes a microcontroller to facilitate data communication within a system comprising a plurality of peripheral devices, a power manager to put the microcontroller into a sleep state to save power, and an I/O controller to enable communication between two or more particular peripheral devices in the plurality of peripheral devices without involvement of the microcontroller while the microcontroller is in the sleep state. The microcontroller is to wake from the sleep state in response to at least one signal from a component of the system external to the microcontroller and communication between at least some of the plurality of peripheral devices is facilitated using the microcontroller when in an awake state.