公开(公告)号：JP2009295156A

公开(公告)日：2009-12-17

申请号：JP2009124745

申请日：2009-05-22

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： KURTS TSVIKA ,  CHENG KAI ,  GILBERT JEFFREY D ,  MANDELBLAT JULIUS

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0831 ,  G06F12/082

Abstract: PROBLEM TO BE SOLVED: To solve a problem, when a cache line in one cache level or snoop filter is evicted, the cache line corresponding to another level of a cache hierarchy is evicted in order to keep the cache hierarchy, and, when the snoop filter transmits many such requests, the interconnection bandwidth of increasing an effective memory latency is consumed and useful cache entry is removed. SOLUTION: This removing method includes steps of: receiving an indication of a pending capacity eviction from a caching agent; determining whether an invalidating write back transaction from the caching agent is likely for a cache line associated with the pending capacity eviction; and, if so, moving a snoop filter entry associated with the cache line from the snoop filter to a staging area. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题为了解决问题，当一个高速缓存级别或窥探过滤器中的高速缓存行被驱逐时，与缓存层级的另一个级别相对应的高速缓存行被驱逐以便保持高速缓存层级， 当窥探过滤器发送许多这样的请求时，消耗增加有效存储器延迟的互连带宽，并且消除有用的高速缓存条目。 解决方案：该移除方法包括以下步骤：从缓存代理接收待处理容量迁移的指示; 确定来自高速缓存代理的无效的回写事务是否可能用于与待处理的容量迁移相关联的高速缓存行; 并且如果是，则将与高速缓存行相关联的窥探过滤条目从窥探过滤器移动到暂存区域。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：WO2004061690A2

公开(公告)日：2004-07-22

申请号：PCT/US0339634

申请日：2003-12-12

Applicant: INTEL CORP

Inventor： KURTS TSVIKA ,  WAYNER ZELIG ,  BOJAN TOMMY

IPC: H03K17/16 ,  H04L25/02 ,  G06F13/38

CPC classification number: H04L25/0278 ,  H03K17/164

Abstract: A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

Abstract translation: 确定将终端电路更好地匹配总线信号线的特性阻抗的值。 还决定了当总线（包括线路，正在由其正常工作模式使用的总线）将可用于在安静周期中调整终端电路时，至少基于以下知识： 总线协议和跟踪某些总线协议事件。 在安静周期期间，根据确定的值调节终端电路。

公开(公告)号：WO2004053706A2

公开(公告)日：2004-06-24

申请号：PCT/US0337614

申请日：2003-11-24

Applicant: INTEL CORP

Inventor： KURTS TSVIKA ,  ORENSTIEN DORON ,  YUFFE MARCELO

IPC: G06F1/26 ,  G06F1/32 ,  G06F13/00 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4208 ,  G06F1/3215 ,  G06F1/3253 ,  G06F13/4068 ,  Y02D10/151

Abstract: Various devices and methods are described. According to a first method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus: data sense amplifiers are enabled in response to an address strobe being asserted. The data sense amplifiers are then disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the front side bus. According to a second method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus and address sense amplifiers that receive an address from an address bus portion of the front side bus: address sense amplifiers are enabled in response to a request indication being asserted. The data sense amplifiers are enabled in response to an address strobe being asserted. The address sense amplifiers are disabled in response to the request indication being de-asserted. The address sense amplifiers are disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the data bus.

Abstract translation: 描述了各种设备和方法。 根据由具有从前端总线的数据总线部分接收数据的数据读出放大器的处理器执行的第一种方法：数据读出放大器响应于地址选通被断言而被使能。 至少响应于队列为空而使数据读出放大器失效。 队列跟踪事务，但是要通过前端总线执行。 根据由处理器执行的第二种方法，该处理器具有从前端总线的数据总线部分接收数据的数据读出放大器和从前端总线的地址总线部分接收地址的地址读出放大器：地址读出放大器被使能 响应于请求指示被声明。 响应于地址选通被断言，数据读出放大器被使能。 响应于请求指示被解除断言，地址读出放大器被禁用。 至少响应于队列为空而禁用地址读出放大器。 队列跟踪事务，但是要通过数据总线执行。

公开(公告)号：WO2007078701A3

公开(公告)日：2008-01-03

申请号：PCT/US2006047301

申请日：2006-12-11

Applicant: INTEL CORP ,  KURTS TSVIKA ,  MEHALEL MOTY ,  MANDELBLAT JULIUS ,  GENDLER ALEXANDER

Inventor： KURTS TSVIKA ,  MEHALEL MOTY ,  MANDELBLAT JULIUS ,  GENDLER ALEXANDER

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0742 ,  G06F11/076 ,  G06F11/1064

Abstract: Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Abstract translation: 简而言之，一种方法，主处理单元和计算机系统，分别通过一行更新第一和第二计数器以及一行中的位故障的第二次校正来报告存储器线路中的故障。 在线路中的位故障第三次校正之后，第一和第二计数器的更新被禁用。

公开(公告)号：WO2005117114A3

公开(公告)日：2005-12-29

申请号：PCT/US2005014882

申请日：2005-04-29

Applicant: INTEL CORP ,  KURTS TSVIKA ,  WAIZMAN ALEX ,  YUFFE MARCELO ,  SHMUELY ZIV

Inventor： KURTS TSVIKA ,  WAIZMAN ALEX ,  YUFFE MARCELO ,  SHMUELY ZIV

IPC: G11C17/00 ,  H01L23/50 ,  H01L23/525 ,  G11C5/06

CPC classification number: G11C17/00 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2224/16 ,  H01L2924/01057 ,  H01L2924/3011

Abstract: Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particular embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routers one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.

Abstract translation: 方法和系统提供与各种工业标准插座兼容的半导体管芯，其中每种类型的插座由不同的针脚图标识。 在一个实施例中，管芯具有多个信号线，一个或多个表面接触和耦合到信号线和表面接触的一个或多个信号选择器。 每个信号选择器基于编程信号将一个信号线电连接到一个表面触点。 在特定实施例中，每个信号选择器包括多路复用器和熔丝元件，其中多路复用器基于熔丝元件的编程值将其输入端口中的一个路由到其输出端口。 编程值可以由编程信号设置。

公开(公告)号：WO2005038657A3

公开(公告)日：2005-06-16

申请号：PCT/US2004033694

申请日：2004-10-14

Applicant: INTEL CORP

Inventor： KURTS TSVIKA ,  WAYNER ZELIG

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4059

Abstract: A controller having programmable delay cells in its input/output channels may also include respective registers storing digital values that control the time delays introduced by the respective delay cells. The values programmed to the registers may be determined by testing the timing of signals between the controller and one or more devices coupled to the channels. The tests may include setting the registers with test values from a set of sequential test values, driving a particular pattern on the signals from the controller to the one or more devices, and checking whether portions of the pattern are received accurately by the one or more devices. Adjusting the timing of the signals may involve centering of the signals with respect to set up and hold time restrictions.

Abstract translation: 在其输入/输出通道中具有可编程延迟单元的控制器还可以包括存储数字值的各个寄存器，这些数字值控制各个延迟单元引入的时间延迟。 编程到寄存器的值可以通过测试控制器与耦合到通道的一个或多个设备之间的信号的定时来确定。 这些测试可以包括用来自一组顺序测试值的测试值来设置寄存器，驱动来自控制器的信号到一个或多个设备的特定模式，以及检查模式的部分是否被一个或多个 设备。 调整信号的时序可能包括相对于建立和保持时间限制的信号的中心。

公开(公告)号：WO2004053705A3

公开(公告)日：2005-06-09

申请号：PCT/US0335774

申请日：2003-11-10

Applicant: INTEL CORP

Inventor： KURTS TSVIKA ,  ORENSTEIN DORON ,  YUFFE MARCELO

IPC: G06F1/26 ,  G06F1/32 ,  G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An approach for data bus power control. Data input sense amplifiers of a request agent are enabled prior to a data phase of a transaction according to a data bus power control signal. Once enabled, the data input sense amplifiers can capture data provided during the data phase of the read transaction. Accordingly, the data input sense amplifiers of the request agent are disabled according to the power control signal once the data phase of the read transaction is complete.

Abstract translation: 数据总线功率控制方法。 根据数据总线功率控制信号，请求代理的数据输入读出放大器在事务的数据阶段之前被使能。 一旦使能，数据输入读出放大器可以捕获在读取事务的数据阶段期间提供的数据。 因此，一旦读取事务的数据阶段完成，请求代理的数据输入读出放大器根据功率控制信号被禁用。

公开(公告)号：WO0013092A3

公开(公告)日：2000-11-16

申请号：PCT/US9918946

申请日：1999-08-18

Applicant: INTEL CORP

Inventor： KURTS TSVIKA

IPC: G06F13/42 ,  G06F13/36

CPC classification number: G06F13/4208

Abstract: An apparatus for operating a multiplexed 128-bit external bus (120) within a computer system, including arbitration logic (150) that arbitrates between contending address and data requests according to the number of outstanding data and/or snoop transactions on the external bus (120). In response to the outcome of this arbitration, selection logic (148) grants the external bus (120) to either the contending address and data request. The arbitration logic (150) may compare the number of outstanding data transactions to a predetermined data threshold number when performing the arbitration, this data threshold number being dynamically alterable by an application program or operating system so as to optimize external bus throughput under predetermined conditions.

Abstract translation: 一种用于在计算机系统内操作多路复用的128位外部总线（120）的装置，包括根据所述外部总线上的未完成数据和/或窥探事务的数量在竞争地址和数据请求之间进行仲裁的仲裁逻辑（150） 120）。 响应于该仲裁的结果，选择逻辑（148）将外部总线（120）授予竞争地址和数据请求。 仲裁逻辑（150）可以在执行仲裁时将未完成数据事务的数量与预定的数据阈值数进行比较，该数据阈值数可由应用程序或操作系统动态地改变，以便在预定条件下优化外部总线吞吐量。

公开(公告)号：DE60328520D1

公开(公告)日：2009-09-03

申请号：DE60328520

申请日：2003-11-24

Applicant: INTEL CORP

Inventor： KURTS TSVIKA ,  ORENSTIEN DORON ,  YUFFE MARCELO

IPC: G06F1/32 ,  G06F1/26 ,  G06F13/00 ,  G06F13/40 ,  G06F13/42

Abstract: Various devices and methods are described. According to a first method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus: data sense amplifiers are enabled in response to an address strobe being asserted. The data sense amplifiers are then disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the front side bus. According to a second method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus and address sense amplifiers that receive an address from an address bus portion of the front side bus: address sense amplifiers are enabled in response to a request indication being asserted. The data sense amplifiers are enabled in response to an address strobe being asserted.; The address sense amplifiers are disabled in response to the request indication being de-asserted. The address sense amplifiers are disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the data bus.

公开(公告)号：HK1075949A1

公开(公告)日：2005-12-30

申请号：HK05107990

申请日：2005-09-12

Applicant: INTEL CORP

Inventor： KURTS TSVIKA ,  ORENSTIEN DORON ,  YUFFE MARCELO

IPC: G06F20100101 ,  G06F1/26 ,  G06F1/32 ,  G06F13/00 ,  G06F13/40 ,  G06F13/42

Abstract: Various devices and methods are described. According to a first method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus: data sense amplifiers are enabled in response to an address strobe being asserted. The data sense amplifiers are then disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the front side bus. According to a second method performed by a processor having data sense amplifiers that receive data from a data bus portion of a front side bus and address sense amplifiers that receive an address from an address bus portion of the front side bus: address sense amplifiers are enabled in response to a request indication being asserted. The data sense amplifiers are enabled in response to an address strobe being asserted.; The address sense amplifiers are disabled in response to the request indication being de-asserted. The address sense amplifiers are disabled at least in response to a queue being empty. The queue keeps track of transactions yet to be performed over the data bus.