公开(公告)号：JP2010092474A

公开(公告)日：2010-04-22

申请号：JP2009226716

申请日：2009-09-30

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： WHITE BRYAN R ,  MORAN DOUGLAS

IPC: G06F9/48

CPC classification number: G06F1/3203

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for eliminating delay of transaction because there are possibilities that it takes many hours for a processor from the time when it accepts interruption to the time when it returns a notice of completion indicating the acceptance and the transaction after that is delayed.
SOLUTION: The method includes a step of receiving input posttransaction in a processor complex from peripheral devices and a step of determining whether transaction is interruption transaction, routing the transaction into a first queue if the transaction is the interruption transaction, and routing the transaction into a second queue if the transaction is not the interruption transaction.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于消除事务延迟的方法和设备，因为有可能从处理器接受中断到返回完成指示的时间之后需要花费数小时的时间 接受和交易之后延迟。 解决方案：该方法包括在来自外围设备的处理器复合体中接收输入后处理的步骤，以及确定事务是否是中断事务的步骤，如果事务是中断事务，则将事务路由到第一队列，并且将 如果事务不是中断事务，则事务进入第二个队列。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：GB2463800B

公开(公告)日：2012-04-11

申请号：GB0917131

申请日：2009-09-30

Applicant: INTEL CORP

Inventor： WHITE BRYAN R ,  MORAN DOUGLAS

IPC: G06F9/48 ,  G06F13/16 ,  G06F13/24

公开(公告)号：DE102009043411B4

公开(公告)日：2022-08-25

申请号：DE102009043411

申请日：2009-09-29

Applicant: INTEL CORP

Inventor： WHITE BRYAN R ,  MORAN DOUGLAS

IPC: G06F13/26 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/48 ,  G06F13/24 ,  G06F13/30 ,  G06F13/34

Abstract: Verfahren (100), das umfasst:Empfangen (110) einer von einem Peripheriegerät eingehenden geposteten Transaktion, die an einen Controller oder einen Kern eines Prozessorkomplexes gerichtet ist, in einer Warteschlangenstruktur des Prozessorkomplexes undFeststellen (130), ob die eingehende gepostete Transaktion eine Interrupt-Transaktion ist, und, wenn dies der Fall ist, das Weiterleiten (140) der Interrupt-Transaktion zu einer ersten Warteschlange und anderenfalls das Weiterleiten (135) der eingehenden geposteten Transaktion zu einer zweiten Warteschlange des Prozessorkomplexes, wobei das Weiterleiten der Interrupt-Transaktion zu der ersten Warteschlange ermöglicht, dass eingehende gepostete Nichtinterrupt-Transaktionen und nichtgepostete Transaktionen die Interrupt-Transaktion überholen, wenn sich mindestens ein Teil des Prozessorkomplexes in einem Energiesparzustand befindet.

公开(公告)号：GB2497224A

公开(公告)日：2013-06-05

申请号：GB201302491

申请日：2011-09-12

Applicant: INTEL CORP

Inventor： WISHMAN ALLEN R ,  GHETIE SERGLU D ,  MEVERGNIE MICHAEL NEVE DE ,  WARRIER ULHAS S ,  KARRAR ADIL ,  MORAN DOUGLAS ,  BRANNOCK KIRK D

IPC: G06F21/57 ,  G06F9/445

Abstract: A method, apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the method includes is a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure.

公开(公告)号：DE102009043411A1

公开(公告)日：2010-04-22

申请号：DE102009043411

申请日：2009-09-29

Applicant: INTEL CORP

Inventor： WHITE BRYAN R ,  MORAN DOUGLAS

IPC: G06F13/24

公开(公告)号：GB2463800A

公开(公告)日：2010-03-31

申请号：GB0917131

申请日：2009-09-30

Applicant: INTEL CORP

Inventor： WHITE BRYAN R ,  MORAN DOUGLAS

IPC: G06F9/48 ,  G06F13/16 ,  G06F13/24

Abstract: A method of routing interrupt transactions received in a processor complex from a peripheral device (110) comprises determining if an incoming posted transaction (one that requires no response on completion) is an interrupt transaction (130) and routing it to a first queue (140) or otherwise in which case the transaction is routed to a second queue (135). The first queue may be a dedicated portion of system memory. Preferably, by routing the interrupt transaction to the first queue (135), non interrupt posted and non-posted transactions are allowed to pass the interrupt transaction when a processor is in a low power mode. A second later posted transaction may pass the interrupt transaction but not the first posted transaction according to ordering rules. The posted transaction in the second queue may be handled whilst the interrupt transaction is stored in the first queue due to the low power state of an advanced programmable interrupt controller (APIC). The APIC may be activated when a first interrupt transaction is written to the first queue. The interrupt transaction may be a virtual legacy wire interrupt. The method is to avoid underflow conditions in the peripheral device when a portion of the processor complex is in a low power or powered off state.