公开(公告)号：JPH05210593A

公开(公告)日：1993-08-20

申请号：JP30059892

申请日：1992-10-14

Applicant: INTEL CORP

Inventor： GERII ENU HAMONDO ,  PURADEIIPU DABEI

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/12

Abstract: PURPOSE: To provide a memory device in which the speed and efficiency of data access can be improved by providing a descriptor cache which holds a descriptor so that access to an arranged and tested descriptor can be performed by the same descriptor afterwards. CONSTITUTION: An address generation process includes the change of a present segment for designating a chart based on selection by a selector 501, and the setting of an execution address to the index value of the selector 501. A descriptor can be fetched from a memory 500 by an actual value, and held in an arranging device 550 and a descriptor tester 540, and the descriptor is inspected and the access to the segment is controlled by the descriptor tester 540,. When the disturbance of the access occurs, a failure occurs in a processor. When the disturbance of the access does not occur, the arrange device 550 converts the descriptor into a state in which the descriptor inside is arranged. Then, the successful descriptor is loaded to a segment transistor, and updated to a descriptor cache 570 in order to be used afterwards.

公开(公告)号：JPH05216766A

公开(公告)日：1993-08-27

申请号：JP30059992

申请日：1992-10-14

Applicant: INTEL CORP

Inventor： GERII ENU HAMONDO ,  PURADEIIPU DABEI ,  MUSUTAFUIZU AARU CHIYOUDOFURII

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/12

Abstract: PURPOSE: To obtain an improved memory managing device in which the coherence of a memory can be improved. CONSTITUTION: This is a memory managing device for a computer in which coherence between a descriptor cache and a data cache is held by an inclusive bit mechanism. When a descriptor in a data cache in which an inclusive bit is set to the descriptor corresponding to the descriptor cached in a descriptor cache 570 is changed, the overall descriptor cache 570 is always flashed by the set inclusive bit. Moreover, an effective bit is set to the descriptor in data cache cached from a descriptor chart. When the descriptor to which the effective bit is set in the data cache in the descriptor chart is corrected, the overall descriptor cache 570 is always flashed. Therefore, cache coherence among the descriptor cache 570, data cache, and descriptor chart can be maintained in this improved memory managing device.