公开(公告)号：JP2014182800A

公开(公告)日：2014-09-29

申请号：JP2014032531

申请日：2014-02-24

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE

IPC: G06F9/305 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30149

Abstract: PROBLEM TO BE SOLVED: To provide systems, methods and apparatuses for execution of an instruction that uses a control vector to zero out bits starting at a specific position in each data element of a source in a SIMD processing system.SOLUTION: The execution of a VPBZHI causes, on a per data element basis of a second source, a zeroing of bits higher (more significant) than a starting point in the data element. The starting point is defined by the contents of a data element in a first source. The resultant data elements are stored in a corresponding data element position of a destination.

Abstract translation: 要解决的问题：提供用于执行使用控制向量的指令的系统，方法和装置，用于将从SIMD处理系统中的源的每个数据元素中的特定位置开始的位清零。解决方案：执行 VPBZHI在第二个源的每个数据元素的基础上导致比数据元素中的起始点更高（更重要）的位的归零。 起始点由第一个数据元素的内容定义。 所得数据元素存储在目的地的相应数据元素位置。

公开(公告)号：JP2014089699A

公开(公告)日：2014-05-15

申请号：JP2013199971

申请日：2013-09-26

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： TAL ULIEL ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/315

CPC classification number: G06F15/8076 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/62

Abstract: PROBLEM TO BE SOLVED: To provide vector compress and rotate functionality capable of increasing performance and instruction throughput, and decreasing power use.SOLUTION: In response to an instruction specifying a vector source operand, a mask register, a vector destination operand and a vector destination offset, a mask is read, and corresponding unmasked vector elements are copied from a vector source to adjacent sequential locations in a vector destination, starting at a vector destination offset location.

Abstract translation: 要解决的问题：提供能够提高性能和指令吞吐量以及降低功耗的向量压缩和旋转功能。解决方案：响应于指定向量源操作数的指令，掩码寄存器，向量目标操作数和向量目标 偏移，读取掩码，并且将相应的未屏蔽向量元素从向量源复制到向量目的地中的相邻顺序位置，从向量目的地偏移位置开始。

公开(公告)号：JP2014194753A

公开(公告)日：2014-10-09

申请号：JP2014026125

申请日：2014-02-14

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LOKTYUKHIN MAXIM ,  ROBERT VALENTINE ,  JULIAN C HORN ,  MARK J CHARNEY

IPC: G06F9/30 ,  G06F9/308 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/30029 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/3836

Abstract: PROBLEM TO BE SOLVED: To provide instructions and logic that can fuse OR-test and AND-test functionality on multiple test sources.SOLUTION: A test instruction specifies first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between data from the third source data operand and the result of the first logical operation, to set a condition flag. Some embodiments generate a fused test instruction by dynamically fusing one logical instruction with a test instruction. Other embodiments generate a test instruction through a just-in-time compiler. Some embodiments further fuse a test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.

Abstract translation: 要解决的问题：提供可以在多个测试源上融合OR测试和和测试功能的指令和逻辑。解决方案：测试指令指定第一，第二和第三个源数据操作数以及操作类型。 执行单元响应于解码的测试指令，根据指定的操作类型在来自第一和第二源数据操作数的数据之间执行一个逻辑操作，并且在来自第三源数据操作数的数据与结果之间执行第二逻辑运算 的第一个逻辑操作，设置条件标志。 一些实施例通过将一个逻辑指令与测试指令动态融合来产生融合测试指令。 其他实施例通过即时编译器生成测试指令。 一些实施例进一步使测试指令与随后的条件分支指令融合，并且根据条件标志的设置来执行分支。

公开(公告)号：JP2014182807A

公开(公告)日：2014-09-29

申请号：JP2014042958

申请日：2014-03-05

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： ROBERT VALENTINE ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/355 ,  G06F9/3887 ,  G06F12/023 ,  G06F2212/1044

Abstract: PROBLEM TO BE SOLVED: To access memory locations in only a limited range of a memory in response to a vector memory access instruction.SOLUTION: A processor 100 includes a plurality of packed data registers 107, and also includes execution logic 109 coupled with the packed data registers. The execution logic is operable in response to a limited range vector memory access instruction 103, indicating a source packed memory index having a plurality of packed memory indices selected from 8-bit memory indices and 16-bit memory indices. The execution logic is operable to access memory locations in only a limited range of a memory in response to the limited range vector memory access instruction.

Abstract translation: 要解决的问题：响应于向量存储器访问指令，仅在存储器的有限范围内访问存储器位置。解决方案：处理器100包括多个打包数据寄存器107，并且还包括执行逻辑109与打包的 数据寄存器 执行逻辑可响应于有限范围向量存储器访问指令103而操作，指示源打包存储器索引具有从8位存储器索引和16位存储器索引中选择的多个打包存储器索引。 执行逻辑可操作以响应于有限范围向量存储器访问指令在存储器的有限范围内访问存储器位置。

公开(公告)号：JP2014194755A

公开(公告)日：2014-10-09

申请号：JP2014028261

申请日：2014-02-18

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LOKTYUKHIN MAXIM ,  ROBERT VALENTINE ,  JULIAN C HORN ,  MARK J CHARNEY

IPC: G06F9/318 ,  G06F9/30

CPC classification number: G06F9/30196 ,  G06F8/52 ,  G06F9/30029 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/4552

Abstract: PROBLEM TO BE SOLVED: To provide methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources.SOLUTION: A methods for fusing instructions in a processor includes: fetching a plurality of instructions, including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition; and fusing a portion of the plurality of instructions into a single micro-operation, the portion including both the first and second instructions if the first operand destination and the second operand source are the same and the branch condition is dependent upon the second instruction.

Abstract translation: 要解决的问题：提供用于融合指令以在多个测试源上提供OR测试和与测试功能的方法和装置。解决方案：一种用于在处理器中融合指令的方法，包括：获取多个指令，包括第一指令 指定第一操作数目的地，指定第二操作数源的第二指令和指定分支条件的第三指令; 以及将所述多个指令的一部分融合为单个微操作，如果所述第一操作数目的地和所述第二操作数源相同，则所述部分包括所述第一和第二指令，并且所述分支条件取决于所述第二指令。

公开(公告)号：JP2014182796A

公开(公告)日：2014-09-29

申请号：JP2014028431

申请日：2014-02-18

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： CHRISTOPHER J HUGHES ,  MARK J CHARNEY ,  JESUS CORBAL ,  MILIND B GIRKAR ,  ELMOUSTAPHA OULD-AHMED-VALL ,  TOLL BRET L ,  ROBERT VALENTINE

IPC: G06F9/305 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30152 ,  G06F9/30018 ,  G06F9/30036

Abstract: PROBLEM TO BE SOLVED: To provide common operation means which in general makes it possible to adjust mask bits within writemask registers that correspond to elements in a vector register referred to in a SIMD operation instruction.SOLUTION: The execution of a KZBTZ detects a trailing least significant zero bit position in a first input mask and sets an output mask to have values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in a first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask.

Abstract translation: 要解决的问题：提供通用操作装置，其通常使得可以调整写入掩码寄存器中对应于在SIMD操作指令中引用的向量寄存器中的元素的掩码位。解决方案：KZBTZ的执行检测到最小值 在第一输入掩码中显着的零位位置并且将输出掩模设置为具有第一输入掩码的值，但是与所设置的第一输入掩码中的尾随最低有效零位位置相比，所有位位置接近最高有效位位置 零。 在一些实施例中，使用第二输入掩码作为写掩码，使得根据第二输入掩码中的相应位位置，在尾随最低有效零位位置计算中不考虑第一输入掩码的位位置。

公开(公告)号：BR112015029810A2

公开(公告)日：2017-07-25

申请号：BR112015029810

申请日：2014-06-17

Applicant: INTEL CORP

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE

IPC: G06F9/06 ,  G06F9/30

Abstract: “aparelho e método para reverter e permutar bits em um registro de máscara” trata-se de um aparelho e método para realizar uma reversão de bit e permutação em valores de máscara. por exemplo, um processador é descrito para executar uma instrução a fim de realizar as operações de: ler uma pluralidade de bits de máscara armazenada em um registro de máscara de fonte, em que os bits de máscara são associados aos elementos de dados de vetor de um registro de vetor; e realizar uma operação de reversão de bit para copiar cada bit de máscara de um registro de máscara de fonte para um registro de máscara de destinação, em que a operação de reversão de bit faz com que os bits do registro de máscara de fonte sejam revertidos dentro do registro de máscara de destinação resultando em uma imagem espelhada simétrica da disposição de bit original.

公开(公告)号：GB2518104B

公开(公告)日：2020-07-01

申请号：GB201500433

申请日：2013-06-25

Applicant: INTEL CORP

Inventor： MIKHAIL PLOTNIKOV ,  IGOR ERMOLAEV ,  ANDREY NARAIKIN ,  ROBERT VALENTINE

IPC: G06F9/315 ,  G06F9/30 ,  G06F9/32

Abstract: A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.

公开(公告)号：BR112017011115A2

公开(公告)日：2017-12-26

申请号：BR112017011115

申请日：2015-11-25

Applicant: INTEL CORP

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  GUILLEM SOLE ,  JESUS CORBAL ,  MARK J CHARNEY ,  ROBERT VALENTINE ,  ROGER ESPASA

IPC: G06F9/30

Abstract: ?método e aparelho para realizar uma coleta de bit de vetor? trata-se de um aparelho e método para realizar uma coleta de bit de vetor. por exemplo, uma modalidade de um processador compreende: um primeiro registro de vetor para armazenar um ou mais elementos de dados de origem; um segundo registro de vetor para armazenar um ou mais elementos de controle, em que cada um dentre os elementos de controle compreende uma pluralidade de campos de bit, em que cada campo de bit deve ser associado a uma posição de bit correspondente em um registro de vetor de destino e para identificar um bit a partir de um ou mais elementos de dados de origem a serem copiados para cada uma dentre as posições de bit particulares; e lógica de coleta de bit de vetor para ler cada campo de bit do segundo registro de vetor para identificar um bit a partir de um ou mais elementos de dados de origem e para copiar de modo responsivo o bit de cada um dentre os um ou mais elementos de dados de origem para cada uma dentre as posições de bit correspondentes no registro de vetor de destino.

公开(公告)号：BRPI0920782B1

公开(公告)日：2020-04-22

申请号：BRPI0920782

申请日：2009-10-27

Applicant: INTEL CORP

Inventor： IDO OUZIEL ,  LIHU RAPPOPORT ,  PANKAJ RAGHUVANSHI ,  ROBERT VALENTINE ,  RON GABOR

IPC: G06F9/06 ,  G06F9/22 ,  G06F9/30

Abstract: aparelho, método e sistema para executar fusão eficiente de instruções. a presente invenção refere-se a uma técnica para propiciar a fusão de instruções eficiente dentro de um sistema de computação. em uma modalidade, uma lógica de processamento retarda o processamento de uma segunda instrução, por um período de tempo limite, se uma primeira instrução dentro de uma fila de instruções for fusível com a segunda instrução.