公开(公告)号：WO2017151229A1

公开(公告)日：2017-09-08

申请号：PCT/US2017/013658

申请日：2017-01-16

Applicant: INTEL CORPORATION

Inventor： COX, Christopher E. ,  BAINS, Kuljit S. ,  MCCALL, James A.

IPC: G06F3/06

Abstract: Examples include techniques for command based on die termination (ODT). In some examples, values are programmed to registers at a memory device to establish one or more internal resistance termination (RTT) settings of ODT at the memory device. Values are also programmed to registers at the memory device to establish one more settings for timing of ODT latency. Programmed values may be changed in order to adjust a signal integrity for the memory device during read or write operations.

Abstract translation: 示例包括基于终止命令（ODT）的命令技术。 在一些示例中，值被编程为在存储器设备处注册以在存储器设备处建立ODT的一个或多个内部电阻终端（RTT）设置。 值也被编程为在存储器设备上注册以建立ODT延迟时间的更多设置。 编程值可能会改变，以便在读取或写入操作期间调整存储器设备的信号完整性。

公开(公告)号：WO2016209556A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/034863

申请日：2016-05-27

Applicant: INTEL CORPORATION

Inventor： TOMISHIMA, Shigeki ,  LU, Shih-Lien ,  BAINS, Kuljit S.

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0685 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/4076

Abstract: A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.

Abstract translation: 存储器件执行内部操作以提供可编程突发长度。 存储器件包括独立且可单独寻址的多个存储体。 存储器设备选择多个存储体以突发序列操作，其中所有选择的存储体基于从相关联的存储器控​​制器发送的命令操作。 响应于接收到访问命令，存储器设备生成多个内部操作以使所有选定的存储体执行访问命令，而不需要来自存储器控制器的多个命令。

公开(公告)号：WO2014098968A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/045439

申请日：2013-06-12

Applicant: INTEL CORPORATION

Inventor： BAINS, Kuljit S. ,  MCCALL, James A.

IPC: G06F13/14 ,  G06F13/16

CPC classification number: G06F12/00 ,  G06F13/4243 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4093

Abstract: Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition.

Abstract translation: 通过命令/地址总线将信息从存储器控制器交换到存储器件的技术和机制。 在一个实施例中，存储器件在第一采样周期期间对命令的第一部分进行采样，并在第二采样周期期间对命令的第二部分进行采样，第一部分和第二部分经由命令/地址总线交换。 第一采样周期和第二采样周期分别与时钟信号的第一次转换和时钟信号的第二转换同时进行。 在另一个实施例中，存储器装置的模式确定第一转变和第二转换之间的关系。

公开(公告)号：WO2023282941A1

公开(公告)日：2023-01-12

申请号：PCT/US2022/021994

申请日：2022-03-25

Applicant: INTEL CORPORATION

Inventor： ZHAO, Chong J. ,  TOMISHIMA, Shigeki ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  ZIAKAS, Dimitrios

IPC: G11C5/06

Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

公开(公告)号：WO2017099906A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/059747

申请日：2016-10-31

Applicant: INTEL CORPORATION

Inventor： BAINS, Kuljit S. ,  FUX, Shay ,  HALBERT, John B.

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

Abstract translation: 实施例通常针对在自刷新模式期间执行附加刷新操作。 存储器设备的实施例包括一个或多个存储体，模式寄存器组，模式寄存器组包括第一组模式寄存器位，以及用于为存储器设备提供控制操作的控制逻辑，所述操作包括用于 一个或多个存储体处于刷新信用模式。 控制逻辑将响应于自刷新命令的接收而执行一个或多个额外刷新周期，自刷新命令用于提供当前刷新状态信息，并且将信息存储在第一组模式寄存器位中 在执行一个或多个额外刷新周期后修改刷新状态。

公开(公告)号：WO2014085267A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071533

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  CHANG, Ge

Inventor： VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  CHANG, Ge

IPC: G11C11/40

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

Abstract translation: 用于为存储器件的多个芯片提供终端的技术和机制。 在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。 在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。 在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。 在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

公开(公告)号：WO2014004010A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/044360

申请日：2013-06-05

Applicant: INTEL CORPORATION

Inventor： BAINS, Kuljit S. ,  HALBERT, John B.

IPC: G11C11/4063 ,  G11C11/4096

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0683 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G06F15/7807 ,  G11C7/1003 ,  G11C7/1021 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097

Abstract: Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

Abstract translation: 内存灵活的命令寻址。 存储器件的实施例包括动态随机存取存储器（DRAM）; 以及与DRAM耦合的系统元件，所述系统元件包括用于控制DRAM的存储器控​​制器。 DRAM包括存储体，总线，总线包括用于接收命令的多个引脚和逻辑，其中逻辑提供用于第一类型的命令的总线的共享操作和接收的第二类型的命令 在第一组引脚上。

公开(公告)号：WO2013095518A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066891

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  RUFF, Klaus J. ,  VERGIS, George ,  SAH, Suneeta

Inventor： BAINS, Kuljit S. ,  RUFF, Klaus J. ,  VERGIS, George ,  SAH, Suneeta

IPC: G06F12/00 ,  G06F11/10 ,  G06F13/14

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract translation: 通过将数据通过地址总线传送到连接到数据总线的设备来读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。

公开(公告)号：WO2017039948A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/045640

申请日：2016-08-04

Applicant: INTEL CORPORATION

Inventor： HALBERT, John B. ,  BAINS, Kuljit S.

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Abstract translation: 错误检查和擦除（ECS）模式使存储器件能够执行错误检查和校正（ECC）并计数错误。 相关联的存储器控​​制器通过触发发送到存储器件的触发器来触发ECS模式。 存储器件包括多个可寻址的存储器位置，其可以被组织成诸如字线的段。 存储器位置存储数据并具有相关联的ECC信息。 在ECS模式中，存储器件读取一个或多个存储器位置，并且基于ECC信息为一个或多个存储器位置执行ECC。 存储器装置对包括指示具有至少阈值数量的错误的段的数量的段计数以及指示任何段中的最大错误数的最大计数的错误信息进行计数。

公开(公告)号：WO2016048494A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/045947

申请日：2015-08-19

Applicant: INTEL CORPORATION

Inventor： HALBERT, John B. ,  CHRISTENSON, Bruce A. ,  BAINS, Kuljit S.

IPC: G11C11/4096 ,  G11C11/401 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

Abstract translation: 用于在存储器控制器和存储器件之间交换信息的技术和机制。 在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。 由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。 在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。