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    TECHNIQUES TO COMPRESS CRYPTOGRAPHIC METADATA FOR MEMORY ENCRYPTION
    2.
    发明申请
    TECHNIQUES TO COMPRESS CRYPTOGRAPHIC METADATA FOR MEMORY ENCRYPTION 审中-公开
    用于存储器加密的压缩密码元数据的技术

    公开(公告)号：WO2017105749A1

    公开(公告)日：2017-06-22

    申请号：PCT/US2016/062467

    申请日：2016-11-17

    Applicant: INTEL CORPORATION

    Inventor： BASAK, Abhishek ,  CHHABRA, Siddhartha ,  OH, Jungju ,  DURHAM, David M.

    IPC: G06F12/0802

    CPC classification number: G06F21/79 ,  G06F3/0623 ,  G06F3/0661 ,  G06F3/0673 ,  G06F7/724 ,  G06F12/0886 ,  G06F12/0891 ,  G06F12/124 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/60 ,  G06F2212/70 ,  H03M13/15 ,  H04L9/0637 ,  H04L9/3242 ,  H04N19/463 ,  H04N19/93

    Abstract: Examples include techniques for compressing counter values included in cryptographic metadata. In some examples, a cache line to fill a cache included in on-die processor memory may be received. The cache arranged to store cryptographic metadata. The cache line includes a counter value generated by a counter. The counter value to serve as version information for a memory encryption scheme to write a data cache line to a memory location of an off-die memory. In some examples, the counter value is compressed based on whether the counter value includes a pattern that matches a given pattern and is then stored to the cache. In some examples, a compression aware and last recently used (LRU) scheme is used to determine whether to evict cryptographic metadata from the cache.

    Abstract translation: 示例包括用于压缩包含在加密元数据中的计数器值的技术。 在一些示例中，可以接收用于填充芯片上处理器存储器中包括的高速缓存的高速缓存行。 缓存被设置为存储加密元数据。 高速缓存行包含由计数器生成的计数器值。 该计数器值用作存储器加密方案的版本信息，以将数据高速缓存行写入到脱模存储器的存储器位置。 在一些示例中，基于计数器值是否包括匹配给定模式的模式并随后将其存储到高速缓存中来压缩计数器值。 在一些示例中，使用压缩感知和上一次最近使用（LRU）方案来确定是否从缓存驱逐加密元数据。

    CRYPTOGRAPHIC COMPUTING IN MULTITENANT ENVIRONMENTS
    4.
    发明申请
    CRYPTOGRAPHIC COMPUTING IN MULTITENANT ENVIRONMENTS 审中-公开

    公开(公告)号：WO2021162792A1

    公开(公告)日：2021-08-19

    申请号：PCT/US2020/067072

    申请日：2020-12-26

    Applicant: INTEL CORPORATION

    Inventor： DURHAM, David M. ,  LEMAY, Michael D. ,  SULTANA, Salmin ,  GREWAL, Karanvir S. ,  KOUNAVIS, Michael E. ,  DEUTSCH, Sergej ,  WEILER, Andrew James ,  BASAK, Abhishek ,  BAUM, Dan ,  GHOSH, Santosh

    IPC: G06F21/78 ,  G06F21/72 ,  G06F12/14 ,  H04L9/06 ,  H04L9/08

    Abstract: A processor, a system, a machine readable medium, and a method. The processor comprises first circuitry to: encrypt a first code image using a first code key; load the encrypted first code image into a memory area allocated in memory for the first code image by an operating system running on the processor; and send to the operating system a substitute key that corresponds to the first code key, wherein the first code key is concealed from the operating system; and an instruction cache including control circuitry; and second circuitry coupled to the instruction cache, the second circuitry to: receive the substitute key from the operating system; in response to a first request from the operating system to execute the first code image to instantiate a first process, perform a first cryptographic function using a hardware key to generate the first code key from the substitute key; and program the control circuitry of the instruction cache with the first code key to enable the first code image to be decrypted using the first code key.

    HEURISTIC AND MACHINE-LEARNING BASED METHODS TO PREVENT FINE-GRAINED CACHE SIDE-CHANNEL ATTACKS
    7.
    发明申请
    HEURISTIC AND MACHINE-LEARNING BASED METHODS TO PREVENT FINE-GRAINED CACHE SIDE-CHANNEL ATTACKS 审中-公开

    公开(公告)号：WO2020005450A1

    公开(公告)日：2020-01-02

    申请号：PCT/US2019/034442

    申请日：2019-05-29

    Applicant: INTEL CORPORATION

    Inventor： BASAK, Abhishek ,  CHEN, Li ,  SAHITA, Ravi

    IPC: G06F12/14 ,  G06F12/0891 ,  G06F21/55

    Abstract: A system may include a processor and a memory, the processor having at least one cache as well as memory access monitoring logic. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line includes several bits for storing information. During normal operation, the memory access monitoring logic may monitor for a memory access pattern indicative of a side-channel attack (e.g., an abnormally large number of recent CLFLUSH instructions). Upon detecting a possible side-channel attack, the memory access monitoring logic may implement one of several mitigation policies, such as, for example, restricting execution of CLFLUSH operations. Due to the nature of cache-timing side-channel attacks, this prevention of CLFLUSH may prevent attackers utilizing such attacks from gleaning meaningful information.

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