公开(公告)号：US10677845B2

公开(公告)日：2020-06-09

申请号：US15447095

申请日：2017-03-01

Applicant: Intel Corporation

Inventor： Abram M. Detofsky ,  Evan M. Fledell ,  Mustapha A. Abdulai ,  John M. Peterson ,  Dinia P. Kitendaugh ,  Pooya Tadayon ,  Jin Pan ,  David Shia

IPC: G01R31/319 ,  G01R31/28

Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

公开(公告)号：US20180252772A1

公开(公告)日：2018-09-06

申请号：US15447095

申请日：2017-03-01

Applicant: Intel Corporation

Inventor： Abram M. Detofsky ,  Evan M. Fledell ,  Mustapha A. Abdulai ,  John M. Peterson ,  Dinia P. Kitendaugh ,  Pooya Tadayon ,  Jin Pan ,  David Shia

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/31908 ,  G01R31/2886 ,  G01R31/31905

Abstract: A testing system and process comprises a converged test platform for structural testing and system testing of an integrated circuit device. The testing system comprises a converged test platform supported by a baseboard of an automated test assembly. The converged test platform comprises a DUT socket for testing an integrated circuit device, at least one testing electronic component selectively electrically coupled to the DUT socket by at least one switch operable to electrically switch at least some testing signals between the automated testing assembly and the DUT socket to the at least one testing electronic component for both structural testing and system testing of the integrated circuit device within the same test flow. The switch(es) and testing electronic component(s) (e.g., an FPGA) can be reprogrammable for testing flexibility and faster through put. Associated processes and methods are provided for both class and system testing using the converged test platform for back-end and front-end testing.

公开(公告)号：US20160299174A1

公开(公告)日：2016-10-13

申请号：US14683742

申请日：2015-04-10

Applicant: INTEL CORPORATION

Inventor： Jin Pan ,  Jin Yang ,  Erkan Acar

IPC: G01R1/073 ,  G01R3/00 ,  G01R1/04

CPC classification number: G01R3/00 ,  G01R1/07307 ,  G01R1/07314 ,  G01R1/07342 ,  G01R1/07378 ,  G01R31/2889

Abstract: A microelectronic test device comprising an organic substrate, a probe holder, and an interposer disposed between the organic substrate and the probe holder, wherein the interposer has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the organic substrate. The interposer may effectively decouple the organic substrate from probes in the probe holder, which may substantially reduce or eliminate probe misalignment due to the coefficient of thermal expansion mismatch between the organic substrate and other components of the microelectronic test device and to provide require stiffness to the organic substrate.

Abstract translation: 一种微电子测试装置，包括有机衬底，探针保持器和设置在有机衬底和探针支架之间的插入器，其中插入器的热膨胀系数小于有机衬底的热膨胀系数。 插入器可以有效地将有机衬底与探针保持器中的探针分离，这可以由于有机衬底和微电子测试装置的其它部件之间的热膨胀失配系数而大大减少或消除探针不对准，并且为 有机底物。

公开(公告)号：US10469181B2

公开(公告)日：2019-11-05

申请号：US15993890

申请日：2018-05-31

Applicant: Intel Corporation

Inventor： Jin Pan ,  Erkan Acar ,  Stephen S. Sturges

IPC: H04B17/00 ,  H04B17/15 ,  H04B17/29

Abstract: A test apparatus and method of testing a DUT are described. The apparatus includes a receiver and transmitter path each having a pair of switches that switch between a bypass position and a direct position. The bypass position is used for low frequency signals communicated through the apparatus. The direct position allows higher frequency signals to be double converted by upconversion to an IF signal and bandpass filtered before being downconverted to a predetermined frequency. Both variable and fixed LO signals are used to convert the double converted signals so that the same IF may be used independent of the higher frequency signal received or transmitted. Bandpass filtering is applied before and after amplification of the IF signal. Lowpass filtering before and after the double conversion use LPFs of different cutoff frequencies.

公开(公告)号：US10101367B2

公开(公告)日：2018-10-16

申请号：US14683742

申请日：2015-04-10

Applicant: INTEL CORPORATION

Inventor： Jin Pan ,  Jin Yang ,  Erkan Acar

IPC: G01R3/00 ,  G01R1/073 ,  G01R31/28

Abstract: A microelectronic test device comprising an organic substrate, a probe holder, and an interposer disposed between the organic substrate and the probe holder, wherein the interposer has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the organic substrate. The interposer may effectively decouple the organic substrate from probes in the probe holder, which may substantially reduce or eliminate probe misalignment due to the coefficient of thermal expansion mismatch between the organic substrate and other components of the microelectronic test device and to provide require stiffness to the organic substrate.

公开(公告)号：US20180188288A1

公开(公告)日：2018-07-05

申请号：US15393640

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Erkan Acar ,  Abram M. Detofsky ,  Jin Pan

IPC: G01R1/04 ,  G01R31/28

Abstract: In one embodiment, a device to test one or more electronic components comprises a first card comprising a first test device communicatively coupled to at least a first connector assembly positioned on the first card and a second card comprising a second test device communicatively coupled to at least a second connector assembly positioned on the second card. The at least a first connector assembly is directly communicatively coupled to the at least a second connector assembly to provide a direct communication interface between the first test device and the second test device that is not routed via a backplane. Other embodiments may be described.

公开(公告)号：US08963135B2

公开(公告)日：2015-02-24

申请号：US13690407

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Robert L. Sankman ,  Raseong Kim ,  Jin Pan

IPC: H01L29/08 ,  G06F19/00 ,  H05K3/46 ,  H05K1/00 ,  H01L51/00 ,  H01L27/06 ,  H01L27/28

CPC classification number: H05K3/4644 ,  B29C64/00 ,  B32B27/06 ,  B32B2457/00 ,  B33Y50/02 ,  B33Y70/00 ,  B33Y80/00 ,  H01L27/0688 ,  H01L27/281 ,  H01L51/0004 ,  H05K1/00

Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.

Abstract translation: 描述了包括半导体有机材料在内的三维集成电路。 在一些实施例中，三维集成电路包括一个或多个电子部件，其包括由一个或多个半导体有机材料形成的半导体区域。 三维集成电路的电子部件还可以包括由有机绝缘材料形成的绝缘区域，并且由导电材料形成导电区域。 三维集成电路可以通过诸如三维印刷之类的添加剂制造工艺形成。 还描述了用于生产和测试三维集成电路的装置和方法。