公开(公告)号：US10707319B2

公开(公告)日：2020-07-07

申请号：US15067047

申请日：2016-03-10

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.

公开(公告)号：US09806195B2

公开(公告)日：2017-10-31

申请号：US15069726

申请日：2016-03-14

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US09748391B2

公开(公告)日：2017-08-29

申请号：US15442087

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L29/45 ,  H01L29/207 ,  H01L29/51 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US09548363B2

公开(公告)日：2017-01-17

申请号：US14302371

申请日：2014-06-11

Applicant: Intel Corporation

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Majumdar Amian ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract translation: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

公开(公告)号：US20160284847A1

公开(公告)日：2016-09-29

申请号：US15179884

申请日：2016-06-10

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L29/267 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L29/207 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US09368583B2

公开(公告)日：2016-06-14

申请号：US14702608

申请日：2015-05-01

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/201 ,  H01L29/06 ,  H01L29/207 ,  H01L29/10 ,  H01L29/51 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US08933458B2

公开(公告)日：2015-01-13

申请号：US14048923

申请日：2013-10-08

Applicant: Intel Corporation

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/10 ,  H01L29/76 ,  H01L29/04 ,  H01L21/306 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Abstract translation: 描述了半导体膜的图案化方法。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

公开(公告)号：US11031482B2

公开(公告)日：2021-06-08

申请号：US16889680

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. Vacancies in the gate dielectric layer may be filled with capping layer material.

公开(公告)号：US09691856B2

公开(公告)日：2017-06-27

申请号：US14977479

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/15 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/51 ,  H01L29/12 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

公开(公告)号：US09614083B2

公开(公告)日：2017-04-04

申请号：US15179884

申请日：2016-06-10

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/267 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08 ,  H01L29/201 ,  H01L29/207 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.