公开(公告)号：WO2013101437A1

公开(公告)日：2013-07-04

申请号：PCT/US2012/068682

申请日：2012-12-10

Applicant: INTEL CORPORATION

Inventor： KABURLASOS, Nikos ,  SAMSON, Eirc C.

IPC: G06F1/26 ,  G06F1/04 ,  G06F9/46

CPC classification number: G06F1/3203 ,  G06F9/5044 ,  G06T1/20

Abstract: A method includes executing a workload on a graphics (GFX) core in a first mode the GFX core comprising a plurality of Subslices wherein each of the plurality of Subslices dissipates power. The method further includes calculating a number of clock cycles, Tfirst mode, required for the GFX core to perform the workload in the first mode during a first decision window comprising a plurality of clock cycles and calculating a number of clock cycles, Tsecond mode, required for the GFX core to perform the workload in a second mode during the first decision window wherein the second mode comprises executing the workload with fewer of the plurality of Subslices receiving power than when executing the workload in the first mode. It is then determined, based in part upon Tfirst mode and Tsecond mode, if an energy savings is possible by transitioning the GFX core to the second mode.

Abstract translation: 一种方法包括在第一模式中执行在图形（GFX）核心上的工作量，所述GFX核心包括多个子片段，其中所述多个子片段中的每一个耗散功率。 该方法还包括计算在包括多个时钟周期的第一判定窗口期间GFX核在第一模式中执行工作负载所需的时钟周期数Tfirst模式，并计算需要的时钟周期数Tsecond模式 所述GFX核心在所述第一决定窗口期间以第二模式执行所述工作负载，其中所述第二模式包括以比在所述第一模式下执行所述工作负载的情况下更少的所述多个子代理接收功率来执行所述工作负载。 然后，部分地基于Tfirst模式和Tsecond模式确定如果通过将GFX核心转换到第二模式可以节省能量。

公开(公告)号：WO2003073113A1

公开(公告)日：2003-09-04

申请号：PCT/US2003/003683

申请日：2003-02-07

Applicant: INTEL CORPORATION

Inventor： KABURLASOS, Nikos ,  LITTLE, James ,  NIKHADE, Vaishali

IPC: G01R31/11

CPC classification number: G01R31/11

Abstract: The invention relates to performing adjustable time domain reflectometry (TDR). A TDR pulse count is set to a predetermined number (704). Next, a TDR pulse is transmitted through a cable (706). The width of the TDR pulse is a function of the multiplication of the TDR pulse count with the period of a TDR clock. It is then determined whether the TDR pulse has been reflected back (708). If the TDR pulse has not been reflected, the TDR pulse count is successively increased (714) to successively increase the width of the transmitted TDR pulse until a reflection is detected indicating an open in the cable (710). Furthermore, embodiments of the invention eliminate false detections of cable opens. Moreover, embodiments of the invention can be combined into a line interface unit (LIU) integrated circuit such that TDR functionality can be performed automatically without the use of a technician.

Abstract translation: 本发明涉及执行可调时域反射计（TDR）。 将TDR脉冲计数设定为预定数（704）。 接下来，TDR脉冲通过电缆（706）传输。 TDR脉冲的宽度是TDR脉冲计数与TDR时钟周期相乘的函数。 然后确定TDR脉冲是否已被反射回来（708）。 如果没有反映TDR脉冲，则TDR脉冲计数被连续地增加（714），以连续地增加发射的TDR脉冲的宽度，直到检测到指示电缆中的开路的反射（710）。 此外，本发明的实施例消除了电缆开口的错误检测。 此外，本发明的实施例可以组合成线路接口单元（LIU）集成电路，使得TDR功能可以在不使用技术人员的情况下自动执行。

公开(公告)号：WO2014074176A1

公开(公告)日：2014-05-15

申请号：PCT/US2013/048037

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： KABURLASOS, Nikos ,  SAMSON, Eric C. ,  KOKER, Altug

IPC: G06F9/50 ,  G06F9/06

CPC classification number: G06T1/20

Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.

Abstract translation: 根据一些实施例，可以通过动态地重新平衡资源之间的工作负载来缓解在图形处理器单元内的特定资源中出现的性能瓶颈，目的是消除当前的性能瓶颈，同时保持当前分配的 电力预算 在一些实施例中，这可以通过为多个图形处理器资源中的每个图形处理器资源定义单独的时钟域来实现，其中性能可以被重新平衡。

公开(公告)号：WO2013077848A1

公开(公告)日：2013-05-30

申请号：PCT/US2011/061738

申请日：2011-11-21

Applicant: INTEL CORPORATION ,  KABURLASOS, Nikos ,  SAMSON, Eric C.

Inventor： KABURLASOS, Nikos ,  SAMSON, Eric C.

IPC: G06F1/26 ,  G06F9/44 ,  G06F9/305

CPC classification number: G06T1/20 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3287 ,  G09G5/36 ,  G09G2360/08 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.

Abstract translation: 功率选通图形处理器的一部分可以用于提高性能或实现功率预算。 可以选择处理器粒度，例如片或子片。

公开(公告)号：WO2023048709A1

公开(公告)日：2023-03-30

申请号：PCT/US2021/051470

申请日：2021-09-22

Applicant: INTEL CORPORATION

Inventor： KABURLASOS, Nikos

IPC: G06F1/3234 ,  G06F1/26 ,  G06F1/3212 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  H02J7/00 ,  H02J7/34

Abstract: An apparatus for managing a power consumption of processor or memory circuitry comprising a plurality of processing or memory functional units may be provided. The processor or memory circuitry is arranged to receive electrical power from an alternating current, AC, power source or a battery. The apparatus comprises processing circuitry to: based on an indication that the processor or memory circuitry is receiving electrical power from the AC power source, selectively cause operational electrical power to be provided to a first number of the functional units of the processor or memory circuitry. The processing circuitry is further to: based on an indication that the circuitry is receiving electrical power from the battery, selectively cause operational electrical power to be provided to a second number of the functional units of the processor or memory circuitry, the second number being less than the first number.

公开(公告)号：WO2016028373A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/036398

申请日：2015-06-18

Applicant: INTEL CORPORATION

Inventor： KABURLASOS, Nikos ,  SAMSON, Eric

IPC: G06T1/20 ,  G06F11/30

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D10/172

Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

Abstract translation: 在一个实施例中，执行单元，图形核心或图形子核心可以在图形操作的框架上动态缩放。 每个图形核心中的可用执行单元可以使用诸如执行单元的当前利用率和提交新的绘制调用之类的利用度量来缩放。 在一个实施例中，基于当前图形操作的集合，可以基于子核的当前或过去利用来启用或禁用每个图形核心内的多个子核中的一个。

公开(公告)号：WO2020205059A1

公开(公告)日：2020-10-08

申请号：PCT/US2020/017279

申请日：2020-02-07

Applicant: INTEL CORPORATION

Inventor： KABURLASOS, Nikos ,  SAMSON, Eric ,  JASOLIYA, Jaymin B.

IPC: G06T1/20 ,  G06T5/20

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.

公开(公告)号：WO2013003255A2

公开(公告)日：2013-01-03

申请号：PCT/US2012/043938

申请日：2012-06-25

Applicant: INTEL CORPORATION ,  KABURLASOS, Nikos ,  SAMSON, Eric C. ,  PUFFER, David ,  JAGANNATHAN, Lakshminarayan

Inventor： KABURLASOS, Nikos ,  SAMSON, Eric C. ,  PUFFER, David ,  JAGANNATHAN, Lakshminarayan

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/08 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.

Abstract translation: 处理器可以在第一时间间隔的第一频率级别操作。 处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。 然后，处理器在第二时间间隔后自动从休眠状态转换到第一频率级。 因此，处理器可以以降低的功率消耗和更高的性能来操作。

公开(公告)号：WO2012112219A2

公开(公告)日：2012-08-23

申请号：PCT/US2011/067580

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  KABURLASOS, Nikos ,  WORRELL, Devon

Inventor： KABURLASOS, Nikos ,  WORRELL, Devon

IPC: G06F9/44 ,  G06F13/38 ,  G06F1/32

CPC classification number: G06F21/84 ,  G06F3/162

Abstract: Methods, systems and computer system products to allow audio decryption and decoding to be performed on a graphics engine instead of on a host processor. This may be accomplished without having to modify media application software. A down codec function driver exposes a down codec to a media application, which may then send encrypted and encoded audio data to the down codec function driver. The down codec function driver may then redirect the audio data to a graphics driver. The graphics driver may then pass the audio data to a graphics engine. The graphics engine may then decrypt and decode the audio data. The decrypted and decoded audio data may be returned to the graphics driver, which may then send the decrypted and decoded audio data to the function driver. The function driver may then pass the decrypted and decoded audio data to the down codec for rendering.

Abstract translation: 方法，系统和计算机系统产品允许音频解码和解码在图形引擎上而不是主机处理器上执行。 这可以在不必修改媒体应用软件的情况下完成。 下行编解码器功能驱动器将下行编解码器公开给媒体应用，然后媒体应用可以将加密和编码的音频数据发送到下行编解码器功能驱动器。 然后，下行编解码器功能驱动器可以将音频数据重定向到图形驱动器。 然后，图形驱动程序可以将音频数据传递给图形引擎。 然后，图形引擎可以对音频数据进行解密和解码。 解密和解码的音频数据可以被返回到图形驱动器，图形驱动器然后可以将解密和解码的音频数据发送到功能驱动器。 然后，功能驱动器可以将解密和解码的音频数据传送到下行编解码器进行渲染。

公开(公告)号：WO2012108934A1

公开(公告)日：2012-08-16

申请号：PCT/US2011/066340

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  KABURLASOS, Nikos ,  BISWAL, Narayan ,  CHENG, Scott W. ,  JIANG, Hong ,  STONER, Michael D.

Inventor： KABURLASOS, Nikos ,  BISWAL, Narayan ,  CHENG, Scott W. ,  JIANG, Hong ,  STONER, Michael D.

IPC: G10L19/00 ,  G11B20/10

CPC classification number: H04N21/4143 ,  H04N19/42 ,  H04N19/44 ,  H04N21/42607 ,  H04N21/42653

Abstract: Techniques are disclosed that involve the processing of audio streams. For instance, a host processing platform may receive a content stream that includes an encoded audio stream. In turn, a graphics engine produces from it a decoded audio stream. This producing may involve the graphics engine performing various operations, such as an entropy decoding operation, an inverse quantization operation, and an inverse discrete cosine transform operation. In embodiments, the content stream may further include an encoded video stream. Thus the graphics engine may produce from it a decoded video stream. This audio and video decoding may be performed in parallel.

Abstract translation: 公开了涉及音频流的处理的技术。 例如，主机处理平台可以接收包括编码音频流的内容流。 反过来，图形引擎从其产生经解码的音频流。 该产生可以涉及执行各种操作的图形引擎，诸如熵解码操作，反量化操作和反离散余弦变换操作。 在实施例中，内容流还可以包括编码视频流。 因此，图形引擎可以从其产生解码的视频流。 该音频和视频解码可以并行执行。