公开(公告)号：WO2019066960A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054588

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： GOGINENI, Sireesha ,  KIM, Andrew ,  SHE, Yong ,  BLUE, Karissa J.

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/12 ,  H01L23/00

Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.