公开(公告)号：WO2016099742A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/060934

申请日：2015-11-16

Applicant: INTEL CORPORATION

Inventor： YAMADA, Koichi ,  BIJLANI, Ashish ,  LU, Jiwei ,  ZHAO, Cheng Yan

IPC: G06F21/12 ,  G06F9/45

CPC classification number: G06F9/3806 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145

Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

Abstract translation: 描述了一种方法。 所述方法包括：在确定所述指令是返回指令之后，接收指令，访问返回高速缓存以加载预测的返回目标地址;在确定所述预测转换的返回目标地址不正确并且执行所述指令之后，在查找表中搜索可执行二进制代码 可执行二进制代码来执行二进制翻译。

公开(公告)号：WO2016209472A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/033936

申请日：2016-05-24

Applicant: INTEL CORPORATION

Inventor： INCE, Tugrul ,  YAMADA, Koichi ,  CAPRIOLI, Paul ,  LU, Jiwei

IPC: G06F9/30 ,  G06F12/08 ,  G06F21/52

CPC classification number: G06F8/52 ,  G06F9/4486 ,  G06F12/08 ,  G06F2212/451

Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.

Abstract translation: 用于阴影堆栈管理的技术包括计算设备，当在翻译的二进制文件中执行转换的调用例程时，将本地返回地址推送到计算设备的本机堆栈，向计算设备的堆栈指针添加恒定偏移量， 对转换后的呼叫目标执行本机调用指令，执行本地调用指令后，从堆栈指针中减去常量偏移量。 执行本地调用指令将转换后的返回地址推送到计算设备的影子栈上。 计算设备可以将阴影栈的两个或多个虚拟存储器页面映射到单个物理存储器页面上。 计算设备可以执行翻译的返回例程，其从本机堆栈弹出本地返回地址，将常量偏移量添加到堆栈指针，并执行本地返回指令。 描述和要求保护其他实施例。

公开(公告)号：WO2016094030A1

公开(公告)日：2016-06-16

申请号：PCT/US2015/060610

申请日：2015-11-13

Applicant: INTEL CORPORATION

Inventor： WU, Keqiang ,  LU, Jiwei ,  LEE, Yong-Fong

IPC: G06F13/16 ,  G06F13/14

CPC classification number: G06F9/30065 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30087 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/825 ,  G06F2201/865 ,  G06F2201/88

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Abstract translation: 一个实施例提供了一种装置。 该装置包括处理器，芯片组，用于存储处理的存储器和逻辑。 处理器包括一个或多个核心，并且是执行该过程。 逻辑是响应于大于检测利用阈值（UT）的平台处理器利用参数（PUP）来获取性能监视数据，至少部分地基于检测到的热功能和 /或检测到的热循环，使用二进制转换修改所识别的自旋循环，以创建经修改的处理部分，并且实现从所识别的旋转循环到修改的处理部分的重定向。

公开(公告)号：WO2014189510A1

公开(公告)日：2014-11-27

申请号：PCT/US2013/042369

申请日：2013-05-23

Applicant: INTEL CORPORATION ,  YAMADA, Koichi ,  SHANMUGAVELAYUTHAM, Palanivelra ,  KRISHNASWAMY, Arvind ,  AGRON, Jason M. ,  LU, Jiwei

Inventor： YAMADA, Koichi ,  SHANMUGAVELAYUTHAM, Palanivelra ,  KRISHNASWAMY, Arvind ,  AGRON, Jason M. ,  LU, Jiwei

IPC: G06F21/50

CPC classification number: G06F9/30058 ,  G06F12/0875 ,  G06F21/54 ,  G06F2212/452

Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及通过在执行期间验证分支指令的目标地址来检测面向返回编程（ROP）攻击的技术。 一种装置包括处理器组件和用于由处理器组件执行的比较组件，用于确定是否存在与包括有效目标地址的表中的例程的转换部分相关联的转移指令的目标地址的匹配有效目标地址 。 描述和要求保护其他实施例。

公开(公告)号：EP3234844A1

公开(公告)日：2017-10-25

申请号：EP15870567.3

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： YAMADA, Koichi ,  BIJLANI, Ashish ,  LU, Jiwei ,  ZHAO, Cheng Yan

IPC: G06F21/12 ,  G06F9/45

CPC classification number: G06F9/3806 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145

Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.

Abstract translation: 描述了一种方法。 该方法包括：在确定该指令是返回指令时，接收指令，访问返回高速缓存以加载预测返回目标地址，在确定预测的已翻译返回目标地址不正确时，在查找表中搜索可执行二进制代码， 可执行的二进制代码来执行二进制转换。

公开(公告)号：EP3014423B1

公开(公告)日：2018-03-07

申请号：EP13887955.6

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： SARKAR, Abhik ,  LU, Jiwei ,  SHANMUGAVELAYUTHAM, Palanivelrajan, Rajan ,  AGRON, Jason, M. ,  YAMADA, Koichi

IPC: G06F9/455 ,  G06F9/445 ,  G06F9/48 ,  G06F12/02 ,  G06F12/0802 ,  G06F9/50

CPC classification number: G06F9/5038 ,  G06F8/61 ,  G06F8/62 ,  G06F9/45516 ,  G06F9/485 ,  G06F9/5016 ,  G06F12/0253 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/60

Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.

公开(公告)号：EP3230878A1

公开(公告)日：2017-10-18

申请号：EP15867831.8

申请日：2015-11-13

Applicant: Intel Corporation

Inventor： WU, Keqiang ,  LU, Jiwei ,  LEE, Yong-Fong

IPC: G06F13/16 ,  G06F13/14

CPC classification number: G06F9/30065 ,  G06F8/52 ,  G06F8/70 ,  G06F9/30087 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/825 ,  G06F2201/865 ,  G06F2201/88

Abstract: One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.

Abstract translation: 一个实施例提供一种装置。 该设备包括处理器，芯片组，存储过程的存储器以及逻辑。 处理器包括一个或多个核心并且将执行该过程。 该逻辑是响应于大于检测利用率阈值（UT）的平台处理器利用率参数（PUP）来获取性能监测数据，至少部分地基于检测到的热函数和 /或检测到的热循环，使用二进制翻译修改所识别的旋转循环以创建经修改的过程部分，并且实现从所识别的自旋循环到经修改的过程部分的重定向。

公开(公告)号：EP3314396B1

公开(公告)日：2020-04-15

申请号：EP16814934.2

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： INCE, Tugrul ,  YAMADA, Koichi ,  CAPRIOLI, Paul ,  LU, Jiwei

IPC: G06F9/30 ,  G06F12/08 ,  G06F21/52

公开(公告)号：EP3314396A1

公开(公告)日：2018-05-02

申请号：EP16814934.2

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： INCE, Tugrul ,  YAMADA, Koichi ,  CAPRIOLI, Paul ,  LU, Jiwei

IPC: G06F9/30 ,  G06F12/08 ,  G06F21/52

CPC classification number: G06F8/52 ,  G06F9/4486 ,  G06F12/08 ,  G06F2212/451

Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.

公开(公告)号：EP3014423A1

公开(公告)日：2016-05-04

申请号：EP13887955.6

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： SARKAR, Abhik ,  LU, Jiwei ,  SHANMUGAVELAYUTHAM, Palanivelrajan, Rajan ,  AGRON, Jason, M. ,  YAMADA, Koichi

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/5038 ,  G06F8/61 ,  G06F8/62 ,  G06F9/45516 ,  G06F9/485 ,  G06F9/5016 ,  G06F12/0253 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/60

Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.