公开(公告)号：WO2015195067A2

公开(公告)日：2015-12-23

申请号：PCT/US2013/048775

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： LEE, Kevin J. ,  KOTHARI, Hiten ,  LYTLE, Wayne M.

CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L2224/1182 ,  H01L2224/13565

Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

Abstract translation: 一个实施例包括半导体装置，其包括：再分配层（RDL），其包括具有两个RDL侧壁的图案化RDL线，所述RDL包括选自包括Cu和Au的材料; 直接接触两个RDL侧壁的保护侧壁; 包括该材料的种子层; 和阻挡层; 其中（a）所述RDL线具有与所述两个RDL侧壁正交并在所述两个RDL侧壁之间延伸的RDL线宽，并且（b）所述种子和阻挡层各自包括平行于并且宽于所述RDL线宽度的宽度。 本文描述了其它实施例。

公开(公告)号：WO2017052570A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052131

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GANESAN, Krishna Prakash ,  SATTIRAJU, Seshu V. ,  LYTLE, Wayne M. ,  SINGH, Gurpreet ,  KOTHARI, Hiten

IPC: H01L21/027

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/31144

Abstract: Technologies for masking the roughness of surfaces that may be provided during the manufacturing of semiconductor devices are described. Such technologies include methods for forming a roughness mask on relatively rough surfaces of a device precursor. In some embodiments, the roughness mask is designed to provide a relatively uniform and/or smooth surface for the deposition of subsequent layers, relative to a relatively rough surface upon which the roughness mask is disposed. In particular, methods of forming roughness masks in vias or trenches formed in composite dielectric materials are described. Semiconductor devices including such roughness masks are also described.

Abstract translation: 描述了在半导体器件的制造期间可能提供的用于掩蔽表面粗糙度的技术。 这些技术包括在器件前体的较粗糙表面上形成粗糙度掩模的方法。 在一些实施例中，粗糙度掩模被设计成提供相对均匀和/或光滑的表面，用于相对于布置粗糙掩模的相对粗糙的表面沉积后续层。 特别地，描述了在复合介电材料中形成的通孔或沟槽中形成粗糙度掩模的方法。 还描述了包括这种粗糙掩模的半导体器件。

公开(公告)号：WO2017039671A1

公开(公告)日：2017-03-09

申请号：PCT/US2015/048324

申请日：2015-09-03

Applicant: INTEL CORPORATION

Inventor： KHIRE, Vaibhav S. ,  GANESAN, Krishna Prakash ,  LYTLE, Wayne M. ,  SATTIRAJU, Seshu V.

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/31

CPC classification number: H01L23/49866 ,  H01L21/311 ,  H01L21/31144 ,  H01L23/49827

Abstract: Embodiments of the present disclosure describe techniques to prevent film cracking in thermally cured dielectric film, and associated configurations. A dielectric film may be formed on a patterned metal layer and a substrate on which the patterned metal layer is disposed. A photo-patterned dielectric resist film may be formed on the dielectric film, while providing an opening in the dielectric resist film over the metal layer. A first curing process may be performed to remove a solvent from the dielectric resist film. An exposed portion of the dielectric film, that is disposed in the opening, may then be removed. A second curing process may be performed after the exposed portion of the dielectric film is removed, to polymerize the dielectric resist film. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了防止热固化的电介质膜中的膜破裂的技术以及相关的构造。 电介质膜可以形成在图案化金属层和其上设置图案化金属层的基板上。 可以在电介质膜上形成光刻图案的电介质抗蚀剂膜，同时在金属层上的介质抗蚀剂膜中提供开口。 可以进行第一固化过程以从介电抗蚀剂膜去除溶剂。 然后可以去除设置在开口中的电介质膜的暴露部分。 可以在去除电介质膜的暴露部分之后进行第二固化工艺，以使介电抗蚀剂膜聚合。 可以描述和/或要求保护其他实施例。