公开(公告)号：WO2014105147A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046822

申请日：2013-06-20

Applicant: INTEL CORPORATION ,  LIN, Kevin L. ,  EID, Faras ,  MA, Qing

Inventor： LIN, Kevin L. ,  EID, Faras ,  MA, Qing

IPC: G01P15/105 ,  G01C19/56 ,  B81B3/00

CPC classification number: G01P15/105 ,  G01P15/08

Abstract: Techniques and mechanisms to provide for metering acceleration. In an embodiment, a microelectromechanical accelerometer includes a magnet, a mass, and a first support beam portion and second support beam portion for suspension of the mass. Resonance frequency characteristics of the first support beam portion and second support beam portion, based on the magnet and a current conducted by the first support beam portion and second support beam portion, are indicative of acceleration of the mass. In another embodiment, the accelerometer further includes a first wire portion and a second wire portion which are each coupled to the mass and further coupled to a respective anchor for exchanging a signal with the first wire portion and the second wire portion. The first wire portion and the second wire portion provide for biasing of the mass.

Abstract translation: 提供计量加速度的技术和机制。 在一个实施例中，微机电加速度计包括用于悬挂质量的磁体，质量块和第一支撑梁部分和第二支撑梁部分。 基于磁体的第一支撑梁部分和第二支撑梁部分的共振频率特性以及由第一支撑梁部分和第二支撑梁部分传导的电流表示质量的加速度。 在另一个实施例中，加速度计还包括第一线部分和第二线部分，每个第一线部分和第二线部分均耦合到质量块，并且还耦合到相应的锚，用于与第一线部分和第二线部分交换信号。 第一线部分和第二线部分提供质量的偏压。

公开(公告)号：WO2014004009A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/044354

申请日：2013-06-05

Applicant: INTEL CORPORATION

Inventor： TEH, Weng Hong ,  LIN, Kevin, L. ,  EID, Feras ,  MA, Qing

IPC: H01L23/62 ,  H01L25/07

CPC classification number: H01L24/19 ,  H01H1/0036 ,  H01H59/0009 ,  H01L23/5382 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A semiconductor package having a mechanical fuse therein and methods to form a semiconductor package having a mechanical fuse therein are described. For example, a semiconductor structure includes a semiconductor package. A semiconductor die is housed in the semiconductor package. A microelectromechanical system (MEMS) device is housed in the semiconductor package. The MEMS device has a suspended portion. A mechanical fuse is housed in the semiconductor package and either coupled to, or decoupled from, the suspended portion of the MEMS device.

Abstract translation: 描述了具有机械熔断器的半导体封装以及形成其中具有机械熔丝的半导体封装的方法。 例如，半导体结构包括半导体封装。 半导体管芯被容纳在半导体封装中。 微机电系统（MEMS）装置容纳在半导体封装中。 MEMS器件具有悬挂部分。 机械保险丝容纳在半导体封装中，并且耦合到MEMS器件的悬置部分或从MEMS器件的悬挂部分解耦。

公开(公告)号：WO2011084216A2

公开(公告)日：2011-07-14

申请号：PCT/US2010/054931

申请日：2010-11-01

Applicant: INTEL CORPORATION ,  MA, Qing ,  HU, Chuan ,  MORROW, Patrick

Inventor： MA, Qing ,  HU, Chuan ,  MORROW, Patrick

IPC: H01L23/485 ,  H05K3/46

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：WO2007002547A3

公开(公告)日：2007-01-04

申请号：PCT/US2006/024722

申请日：2006-06-22

Applicant: INTEL CORPORATION ,  HECK, John ,  MA, Qing ,  TRAN, Quan ,  CHOU, Tsung-Kuan ,  ALTSHULER, Semeon ,  WEINFELD, Boaz

Inventor： HECK, John ,  MA, Qing ,  TRAN, Quan ,  CHOU, Tsung-Kuan ,  ALTSHULER, Semeon ,  WEINFELD, Boaz

IPC: H01L21/768 ,  H01L23/48

Abstract: An apparatus and method of fabricating a through-wafer via. A first mask (310) is formed over a first side of a first semiconductor die (105) to define a first via area. A deep recess (305) is etched through the first semiconductor die in the first via area and a blanket metal layer (405) is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface (505) of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.

公开(公告)号：WO2006012255A1

公开(公告)日：2006-02-02

申请号：PCT/US2005/022359

申请日：2005-06-23

Applicant: INTEL CORPORATION ,  HECK, John ,  MA, Qing ,  BAR-SADEH, Eyal

Inventor： HECK, John ,  MA, Qing ,  BAR-SADEH, Eyal

IPC: B81B7/00

CPC classification number: B81C1/0023 ,  Y10S977/701 ,  Y10S977/724

Abstract: An apparatus may include a first substrate, one or more microelectromechanical systems (MEMS) coupled to the first substrate, a second substrate coupled with the first substrate, and one or more passive components coupled to the second substrate. A method may include aligning a first substrate having one or more MEMS coupled thereto and a second substrate having one or more passive components coupled thereto, and coupling the aligned substrates.

Abstract translation: 装置可以包括第一基板，耦合到第一基板的一个或多个微机电系统（MEMS），与第一基板耦合的第二基板以及耦合到第二基板的一个或多个无源部件。 一种方法可以包括对准具有耦合到其上的一个或多个MEMS的第一基板和具有耦合到其上的一个或多个无源部件的第二基板，以及连接对准的基板。

公开(公告)号：WO2006011968A1

公开(公告)日：2006-02-02

申请号：PCT/US2005/020600

申请日：2005-06-10

Applicant: INTEL CORPORATION ,  RAO, Valluri ,  MA, Qing ,  TRAN, Quan ,  SHIM, Dong ,  WANG, Li-Peng

Inventor： RAO, Valluri ,  MA, Qing ,  TRAN, Quan ,  SHIM, Dong ,  WANG, Li-Peng

IPC: H03H9/02

CPC classification number: H03H9/02102 ,  H03H2009/02196

Abstract: A film bulk acoustic resonator (FBAR) comprises a piezoelectric film sandwiched between a top electrode and a bottom electrode. A temperature sensor is provided to sense a temperature to determine a temperature induced frequency drift for the FBAR. A voltage controller operatively connected to the temperature sensor supplies a direct current (DC) bias voltage to the FBAR to induce an opposite voltage induced frequency drift to compensate for the temperature induced frequency drift.

Abstract translation: 薄膜体声波谐振器（FBAR）包括夹在顶部电极和底部电极之间的压电薄膜。 提供温度传感器以感测温度以确定FBAR的温度感应频率漂移。 可操作地连接到温度传感器的电压控制器向FBAR提供直流（DC）偏置电压，以引起相反的电压感应频率漂移，以补偿温度引起的频率漂移。

公开(公告)号：WO2003084862A2

公开(公告)日：2003-10-16

申请号：PCT/US2003/009620

申请日：2003-03-27

Applicant: INTEL CORPORATION

Inventor： MA, Qing ,  RAO, Valluri ,  WANG, Li-Peng ,  TRAN, Quan ,  HECK, John

IPC: B81C3/00

CPC classification number: B81B7/0006 ,  B81C2203/0118 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (32) may be enclosed in a hermetic cavity (44) defined by joined, first and second semiconductor structures (14, 12). The joined structures (14, 12) may be sealed by a soldier sealing ring (18), which extends completely around the cavity (44). One of the semiconductor structures (14, 12) may have the system (32) formed thereon and an open area (38) may be formed from the underside of the structure (14, 12) and may be closed by covering with a suitable film (20) in one embodiment.

Abstract translation: 微机电系统（32）可封闭在由连接的第一和第二半导体结构（14,12）限定的密封腔（44）中。 接合结构（14,12）可以由完全围绕空腔（44）延伸的士兵密封环（18）密封。 半导体结构（14,12）中的一个可以具有形成在其上的系统（32），并且可以从结构（14,12）的下侧形成开放区域（38），并且可以通过用合适的膜覆盖来封闭 （20）。

公开(公告)号：WO2003002450A2

公开(公告)日：2003-01-09

申请号：PCT/US2002/020764

申请日：2002-06-27

Applicant: INTEL CORPORATION

Inventor： MA, Qing ,  CHENG, Peng

IPC: B81B3/00

CPC classification number: B81C1/00126 ,  B81C2201/0109 ,  H03H3/0072

Abstract: A method comprising over an area of a substrate, forming a plurality of three dimensional first structures; following forming the first structures, conformally introducing a sacrificial material over the area of the substrate; introducing a second structural material over the sacrificial material; and removing the sacrificial material. An apparatus comprising a first structure on a substrate; and a second structure on the substrate and separated from the first structure by an unfilled gap defined by the thickness of a removed film.

Abstract translation: 一种方法，所述方法包括在衬底的区域上方形成多个三维第一结构; 在形成第一结构之后，在衬底的区域上共形地引入牺牲材料; 在牺牲材料上引入第二结构材料; 并去除牺牲材料。 一种装置，包括在衬底上的第一结构; 以及第二结构，该第二结构在基板上并且通过由去除的膜的厚度限定的未填充的间隙与第一结构分开。

公开(公告)号：WO2015094184A1

公开(公告)日：2015-06-25

申请号：PCT/US2013/075764

申请日：2013-12-17

Applicant: INTEL CORPORATION

Inventor： MA, Qing ,  SWAN, Johanna ,  RAO, Valluri ,  EID, Feras

IPC: B81B7/00 ,  H01H51/22 ,  H01H59/00 ,  B81C1/00

CPC classification number: H01H59/0009 ,  H01H50/005 ,  H01H2229/016 ,  H01H2229/05 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01Q5/314

Abstract: An electronic device and methods including a switch formed in a chip package are shown. An electronic device and methods including a switch formed in a polymer based dielectric are shown. Examples of switches shown include microelectromechanical system (MEMS) structures, such as cantilever switches and/or shunt switches.

Abstract translation: 示出了包括形成在芯片封装中的开关的电子装置和方法。 示出了包括形成在基于聚合物的电介质中的开关的电子装置和方法。 所示的开关的示例包括微机电系统（MEMS）结构，例如悬臂开关和/或分流开关。

公开(公告)号：WO2004061882A1

公开(公告)日：2004-07-22

申请号：PCT/US2003/038217

申请日：2003-12-03

Applicant: INTEL CORPORATION

Inventor： ZIPPER, Eliav ,  MA, Qing

IPC: H01H1/00

CPC classification number: H01H9/542 ,  H01H1/0036 ,  H01H9/541 ,  H01H59/0009

Abstract: In a switching scheme mechanical MEMs switches are connected in parallel with solid state switches. This parallel MEMs/solid-state switch arrangement takes advantage of the fast switching speeds of the solid state switches as well advantage of the improved insertion loss and isolation characteristics of the MEMs switches. The solid-state switches only need to be energized during a ramp up/down period associated with the slower MEMs switch thus conserving power. As an additional advantage, using a solid-state switch in parallel with MEMs switches improves the transient spectrum of the system during switching operations.

Abstract translation: 在开关方案中，机械MEMs开关与固态开关并联连接。 这种并行的MEM /固态开关装置利用固态开关的快速开关速度以及MEM开关的改进的插入损耗和隔离特性的优点。 固态开关只需要在与较慢的MEMs开关相关联的斜坡上升/下降周期期间被通电，从而节省功率。 作为额外的优点，与MEMs开关并联的固态开关可以改善开关操作期间系统的瞬态频谱。