公开(公告)号：US11798125B2

公开(公告)日：2023-10-24

申请号：US17828411

申请日：2022-05-31

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC: G06F13/14 ,  G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06T1/60 ,  G06F9/45558 ,  G06F9/4881 ,  G06F9/5038 ,  G06T15/005 ,  G06F2009/45579 ,  G06F2009/45591

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US10387992B2

公开(公告)日：2019-08-20

申请号：US15482680

申请日：2017-04-07

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC: G06T1/00 ,  G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US11354770B2

公开(公告)日：2022-06-07

申请号：US17182256

申请日：2021-02-23

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC: G06F13/14 ,  G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US10937123B2

公开(公告)日：2021-03-02

申请号：US16505555

申请日：2019-07-08

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC: G06F13/14 ,  G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US10417729B2

公开(公告)日：2019-09-17

申请号：US15043018

申请日：2016-02-12

Applicant: INTEL CORPORATION

Inventor： Robert B. Taylor ,  Pankaj Sharma ,  Daniel H. Walsh ,  Matthew B. Callaway

IPC: G06T1/20 ,  G06F9/54

Abstract: Techniques to sort events of a graphics workload executed by a graphics processing unit to provide identification of events, that if addressed, may result in an improvement in performance are disclosed. The techniques can include: generating a signature and a weight for each event of a graphics workload; generating an event priority tree by organizing the events into parent and leaf nodes, where parent nodes comprise leaf nodes having a shared hash; and sorting frames based on a global weight of events corresponding to the frames.